BRANCH-E&TC ENGINEERING

SEM – 5^TH

SUBJECT-VLSI

TOPIC-CMOS

FACULTY-ER S MOHANTA.

Outline

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• CMOS Gate Design
• Pass Transistors
• CMOS Latches & Flip-Flops
• Standard Cell Layouts
• Stick Diagrams

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CMOS Gate Design

• A 4-input CMOS NOR gate

Complementary CMOS

• Complementary CMOS logic gates
• nMOS pull-down network
• pMOS pull-up network
• a.k.a. static CMOS

Series and Parallel

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• nMOS: 1 = ON
• pMOS: 0 = ON
• Series: both must be ON
• Parallel: either can be ON

Conduction Complement

• Complementary CMOS gates always produce 0 or 1

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• Ex: NAND gate
• Series nMOS: Y=0 when both inputs are 1
• Thus Y=1 when either input is 0
• Requires parallel pMOS

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• Rule of Conduction Complements
• Pull-up network is complement of pull-down
• Parallel -> series, series -> parallel

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Compound Gates

• Compound gates can do any inverting function
• Ex: AND-AND-OR-INV (AOI22)

Example: O3AI

Example: O3AI

Pass Transistors

• Transistors can be used as switches

Pass Transistors

• Transistors can be used as switches

Signal Strength

• Strength of signal
• How close it approximates ideal voltage source
• V_DD and GND rails are strongest 1 and 0
• nMOS pass strong 0
• But degraded or weak 1
• pMOS pass strong 1
• But degraded or weak 0
• Thus NMOS are best for pull-down network
• Thus PMOS are best for pull-up network

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Transmission Gates

• Pass transistors produce degraded outputs
• Transmission gates pass both 0 and 1 well

Transmission Gates

• Pass transistors produce degraded outputs
• Transmission gates pass both 0 and 1 well

Tristates

• Tristate buffer produces Z when not enabled

Nonrestoring Tristate

• Transmission gate acts as tristate buffer
• Only two transistors
• But nonrestoring
• Noise on A is passed on to Y (after several stages, the noise may degrade the signal beyond recognition)

Tristate Inverter

• Tristate inverter produces restored output
• Note however that the Tristate buffer
• ignores the conduction complement rule because we want a Z output

Tristate Inverter

• Tristate inverter produces restored output
• Note however that the Tristate buffer
• ignores the conduction complement rule because we want a Z output

Multiplexers

• 2:1 multiplexer chooses between two inputs

Multiplexers

• 2:1 multiplexer chooses between two inputs

Gate-Level Mux Design

• How many transistors are needed?

Gate-Level Mux Design

• How many transistors are needed? 20

Transmission Gate Mux

• Nonrestoring mux uses two transmission gates

Transmission Gate Mux

• Nonrestoring mux uses two transmission gates
• Only 4 transistors

Inverting Mux

• Inverting multiplexer
• Use compound AOI22
• Or pair of tristate inverters
• Essentially the same thing
• Noninverting multiplexer adds an inverter

4:1 Multiplexer

• 4:1 mux chooses one of 4 inputs using two selects

4:1 Multiplexer

• 4:1 mux chooses one of 4 inputs using two selects
• Two levels of 2:1 muxes
• Or four tristates

D Latch

• When CLK = 1, latch is transparent
• Q follows D (a buffer with a Delay)
• When CLK = 0, the latch is opaque
• Q holds its last value independent of D
• a.k.a. transparent latch or level-sensitive latch

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D Latch Design

• Multiplexer chooses D or old Q

Old Q

D Latch Operation

D Flip-flop

• When CLK rises, D is copied to Q
• At all other times, Q holds its value
• a.k.a. positive edge-triggered flip-flop, master-slave flip-flop

D Flip-flop Design

• Built from master and slave D latches

A “negative level-sensitive” latch

A “positive level-sensitive” latch

D Flip-flop Operation

Inverted version of D

Q -> NOT(NOT(QM))

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Holds the last value of NOT(D)

Race Condition

• Back-to-back flops can malfunction from clock skew
• Second flip-flop fires Early
• Sees first flip-flop change and captures its result
• Called hold-time failure or race condition

Nonoverlapping Clocks

• Nonoverlapping clocks can prevent races
• As long as nonoverlap exceeds clock skew
• Good for safe design
• Industry manages skew more carefully instead

Gate Layout

• Layout can be very time consuming
• Design gates to fit together nicely
• Build a library of standard cells
• Must follow a technology rule

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• Standard cell design methodology
• V_DD and GND should abut (standard height)
• Adjacent gates should satisfy design rules
• nMOS at bottom and pMOS at top
• All gates include well and substrate contacts

Example: Inverter

Inverter, contd..

Layout using Electric

Example: NAND3

• Horizontal N-diffusion and p-diffusion strips
• Vertical polysilicon gates
• Metal1 V_DD rail at top
• Metal1 GND rail at bottom
• 32 λ by 40 λ

NAND3 (using Electric), contd.

Stick Diagrams

• Stick diagrams help plan layout quickly
• Need not be to scale
• Draw with color pencils or dry-erase markers

Stick Diagrams

• Stick diagrams help plan layout quickly
• Need not be to scale
• Draw with color pencils or dry-erase markers

Wiring Tracks

• A wiring track is the space required for a wire
• 4 λ width, 4 λ spacing from neighbor = 8 λ pitch
• Transistors also consume one wiring track

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Well spacing

• Wells must surround transistors by 6 λ
• Implies 12 λ between opposite transistor flavors
• Leaves room for one wire track

Area Estimation

• Estimate area by counting wiring tracks
• Multiply by 8 to express in λ

Example: O3AI

• Sketch a stick diagram for O3AI and estimate area

Example: O3AI

• Sketch a stick diagram for O3AI and estimate area

Example: O3AI

• Sketch a stick diagram for O3AI and estimate area