X International conference�“Information Technology and Implementation” (IT&I-2023)�Kyiv, Ukraine
1
Modeling of Multiport Heteroassociative Memory (MBHM) on the Basis of Equivalence Models Implemented on Vector-Matrix Multipliers
Dedicated to the tenth anniversary of the Faculty of Information Technology
Vladimir Krasilenko,
Illia Chikov,
Diana Nikitovych
Vinnytsia National Agrarian University, Vinnytsia, Ukraine
Introduction
The relevance and necessity of researching the processes of natural intelligence, associative processing of information for the purpose of hardware and software implementation of the corresponding mathematical, simulation and physical models of associative memory (AM) is due to the wide application of new solutions in modern intelligent decision support systems, remote monitoring systems, in robots - technical systems of image recognition and identification of various types and for various problem-oriented areas of application.
Information Technology and Implementation, November 20, 2023, Taras Shevchenko National University of Kyiv, Kyiv, Ukraine
Problem Formulation
One of the tasks is the need to develop and simulate such equivalence models of multiport hetero-associative memory, which would be best suited for implementation based on vector-matrix multipliers or vector-matrix equivalents, and to determine the characteristics and indicators of such models and implementations.
Information Technology and Implementation, November 20, 2023, Taras Shevchenko National University of Kyiv, Kyiv, Ukraine
Methods
The results of modeling the processes of hetero-associative letter tuple recognition, performed in Mathcad for two versions of the multi-port heteroassociative memory (MHAM) implementation, confirm their correct functioning, since the correct tuples of all 100 output letters pairwise associated with 100 input letters are formed by the models at the outputs-ports of the MHAM.
Information Technology and Implementation, November 20, 2023, Taras Shevchenko National University of Kyiv, Kyiv, Ukraine
Results
The procedure for entering 128 characters (a fragment with a part of the various letters or symbols entered) is shown in Figure 1. Each character is coded by a byte in accordance with the accepted coding system. The same fragment shows the procedure for entering 100 English letters or symbols that will correspond to 100 input ports, each of which is supplied with a code vector of the corresponding letter or symbol.
Information Technology and Implementation, November 20, 2023, Taras Shevchenko National University of Kyiv, Kyiv, Ukraine
Results
Here we show the formulas we used to simulate the procedures for finding the necessary matrices of normalized equivalences and non-equivalences using two vector-matrix multipliers (VMM) in the first step. Fragments of windows with the results of simulation procedures for calculating the output matrices of normalized equivalences and non-equivalences in the second step are also shown there.
Information Technology and Implementation, November 20, 2023, Taras Shevchenko National University of Kyiv, Kyiv, Ukraine
Results
The formed tuples of symbols-letters, which are shown below, indicate the successful reproduction of all associated pairs, namely the formation of the corresponding next one for each letter from the input tuple.
Information Technology and Implementation, November 20, 2023, Taras Shevchenko National University of Kyiv, Kyiv, Ukraine
Results
Additional experiments showed that the modeled possible options for the implementation of the multi-port heteroassociative memory allow damage to the code vectors by interference within the permissible limits, which does not cause violations of the correct functioning of the multi-port heteroassociative memory .
Information Technology and Implementation, November 20, 2023, Taras Shevchenko National University of Kyiv, Kyiv, Ukraine
Conclusions
As a result of the development and modeling of multi-port heteroassociative memories operating on the basis of equivalence models, the possibilities of implementations of MHAMs based on such hardware and software accelerators with parallel processing as vector-matrix multipliers and vector-matrix equivalents (essentially 2 multipliers) were confirmed, which in addition to their parallel execution of linear-algebraic procedures-operations would be endowed with the possibility of their parallel execution of component-wise nonlinear transformations.
Information Technology and Implementation, November 20, 2023, Taras Shevchenko National University of Kyiv, Kyiv, Ukraine
Thank you for your attention
Information Technology and Implementation, November 20, 2023, Taras Shevchenko National University of Kyiv, Kyiv, Ukraine