PHASE LOCKED LOOP
MODULE-5
PHASE LOCKED LOOP
BLOCK DIAGRAM OF PLL
PHASE DETECTOR
FILTER
VOLTAGE
CONTROLLED
OSCILLATOR
AMPLIFIER
PHASE DETECTOR
PLL
Vi | Vo | Vd | |
L | L | L | |
H | H | L | |
L | H | H | |
H | L | H | |
Vi
Vo
Vd
0
gnd
gnd
gnd
gnd
Vc
L
L
L
H
L
H
H
H
H
L
H
L
H
L
L
L
H
L
H
H
H
L
L
H
Phase Detector
Vi
Vo
Vd
Vi
Vo
Vd
Vc
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
L
H
L
H
L
L
H
Phase Difference=90 degrees
Vi
Vo
Vd
Vc
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
L
H
L
H
L
L
H
Phase Difference > 90 degrees
Vi
Vo
Vd
Vc
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
L
H
L
H
L
L
H
Phase Difference< 90 degrees
Phase-Lock Mode- When the output frequency becomes equal to the input frequency, PLL is said to be in phase lock mode. The feedback loop maintains the lock when the output frequency becomes equal to input frequency.
Frequency in hz
Capture Range
Tracking Range
Performance Parameters of PLL
Loop Gain of PLL
Tracking Range (Hold-in Range)
Tracking Range
����A PLL system with 105kHz input has a VCO with a 100kHz free-running frequency and a 3.3kHz/V sensitivity. The phase detector sensitivity is 0.68V/rad and the amplifier gain is 5. Calculate the loop gain, input/output phase difference, the static error voltage and the VCO control voltage.�
Phase Detector
Vi | Vo | Vd | |
L | L | L | |
H | H | L | |
L | H | H | |
H | L | H | |
Phase Detector
S | R | Q |
1 | 0 | 1 |
0 | 1 | 0 |
0 | 0 | No Chang |
L
L
Output
L
H
L
H
L
L
H
L
H
L
L
L
L
FREQUENCY DETETCTOR
Calculate the tracking range, maximum error voltage and maximum amplifier output voltage for the PLL system.�
Capture Range
Capture Range
LOW PASS FILTER
VOLTAGE CONTROLLED OSCILLATOR