Predicting Post-Route QoR Estimates for HLS Designs using Machine Learning

Pingakshya Goswami

Speaker Info

Name: Pingakshya Goswami

PhD Student, Department of Electrical Engineering

University of Texas at Dallas

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Research Interest:

• ML based Electronic Design Automation
• FPGA Prototyping
• Hardware Accelerator design on FPGA

High Level Synthesis FPGA Design Flow

Specification

C/C++/SystemC

Compile

LLVM IR

Allocation

Scheduling

Binding

RTL Generation

Verilog

Logic Synthesis

Tech Mapping

Optimization

Placement

Routing

Functional

Unit Library

int a, b, c, d;

int p,q;

main(){

p=a*b;

q=p*(c+d);

}

Pareto Optimal Points

Design Space Exploration

High Level Synthesis

• HLS is the technology by which a program written in algorithmic level using high level languages like C, C++ and System C is converted into synthesizable RTL designs.

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• Popular Commercial HLS Tools:
• Vivado HLS
• NEC CyberWorkBench
• Mentor Catapult
• Cadence C2S
• Legup HLS

Characteristics and Implementation Time of ADPCM

FPGA Used: Xilinx Zynq UltraScale+ XCZU7EV

0

ADPCM

HLS

Logic

Synthesis

Physical Design Stage

Run time in

Minutes

5.77

0

Place and Route

3.85

0

Total time ≈ 3500 mins

C-Synthesis

0

3316

adpcm_main

reset

encode

decode

quantl

uppol1

uppol2

upzero

logscl

filtep

scalel

filtez

Quality of Results of a Design

• Latency:  Latency is defined as the number of clock cycles required to produce an output.
• Resource Requirement: # of logic resources. These include
• Flip Flops,
• LUTs,
• BRAM,
• DSPs,
• IOBs used by a design.
• Timing: Delay of the critical path of a circuit. This impacts the maximum frequency of operation.
• Power: Mainly concerned in portable and mobile devices. Smaller technology nodes have higher leakage power.

Vivado HLS vs Post Route Values

Current State of the Art

• COMBA HLS Predict
• Contributions
• Proposed graph based metrics guided DSE.
• Suggests pragmas based on LLVM graphs
• Predicts latency pre-synthesis.

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• Drawbacks
• Predicted only latency
• Compared against Vivado HLS results (no post-route QoR)
• No results about resource and timing predictions.

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Fast & Accurate HLS Predict

Contributions

1. Predicts post route timing and resource requirement
2. Uses features from post synth log files
3. Achieves good accuracy for the predicted parameters

Drawbacks

1. Needs to synthesize designs
2. Did not predict on individual benchmarks
3. Did not predict latency.
4. Calibrates post C-synthesis results tot match post route results.

Pyramid HLS Predict

Contributions

1. Predicts post route resource and timing of HLS designs.
2. Extracts features from HLS log files.
3. Post route labels generated from Minerva tool.

Drawbacks

1. Do not predict latency.
2. Synthesis required to generate features.
3. Did not predict on individual benchmarks.

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J. Zhao, L. Feng, S. Sinha, W. Zhang, Y. Liang and B. He, "COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications," 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

H. M. Makrani, F. Farahmand, .Sayadi, Sara Bondi , S. Dinakarrao, H.Homayoun, S. Rafatiradao, , “Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design,"  arXiv 2019

S. Dai, Y. Zhou, H. Zhang, E. Ustun, E.F. Y. Young, and Z. Zhang. Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. Field Programmable Custom Computing Machines (FCCM), 2018.

Ironman

Contributions

1. Predicts PPA in HLS designs.
2. Extends the same work to ML based DSE.
3. GNN and Reinforcement Learning is used

Drawbacks

1. Needs a Code Transformer to generate scheduled DFG
2. Can predict Resource and Frequency; Not Latency
3. Did not predict on individual benchmarks
4. Use only one pragma

“#pragma HLS allocation instance=mul”.

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Nan Wu, Yuan Xie, and Cong Hao. 2021. “IRONMAN: GNN-assisted Design Space Exploration in HLS using Reinforcement Learning” Proceedings of the 2021 on Great Lakes Symposium on VLSI

Comparison with Existing Works

Problem Statement

Given a dataset of synthesizable C/C++ based HLS code with all the pragma information.

Is it possible to create a machine learning based model which will predict the post route clock period, latency and resource requirement of a design without synthesizing the design

Overview of LLVM

Clang Frontend parser

Optimizer

Tech Specific Backend

• Redundant code removal
• Mem Optimization
• Change in code structure
• Bitwidth reduction

C/C++

IR Code

IR Code

• LLVM is a compiler which converts a high level C/C++ or Python code into technology independent assembly code “Intermediate Representation”.
• LLVM consists of 3 parts:

FPGA HLS Input

Arm assembly

X86 assembly

GPU specific codes

Proposed Flow

Feature Analysis

Callgraph

Control Flow Graph

Data Flow Graph

Graphs in LLVM

Study of Feature Importance

Tool Used: xgboost plot_importance

Selection of Training/Test Data

• Data division : Training 120 designs; Test: 280 designs
• Results shown in Mean Absolute Percentage Error

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Design of Experiments

• M1: Fully Localized Training Model
• Used in Design Space Exploration
• A fraction of DSE designs generated using actual HL synthesis
• Remaining are predicted using fast ML based predictive DSE
• M2: Frequency Sweep Experiment
• Trained on 3 different frequencies with varying pragmas
• Tested on baseline design for 8 different frequencies
• Predicted resource, latency and timing 8 frequencies on baseline design
• M3: Multi FPGA robustness test
• Trained and tested on 3 different FPGA devices
• Trained on 300 versions of adpcm design
• Tested on 64 totally new unseen designs

Analysis of Results

• M1: Fully Localized Training Model
• Mean Absolute Percentage Error Values

Analysis of Results

• M2: Frequency Sweep Experiment
• Actual vs Predicted Values

Analysis of Results

• M3: Multi FPGA Results
• MAPE values using Gradient Boost Regression

Summary and Conclusion

• First work to predict post route matrices without synthesis.
• Tested on 10 benchmarks from Chstone and S2cbench
• Can be easily integrate with commercial HLS tools.
• Achieved MAE of < 10% for all the 3 predicted parameters for all three proposed training methods.
• Proposing to analyze features rigorously to create more robust models.
• Achieved average speed up of 3.48x using fully localized as compared to Vivado HLS results.
• Tested robustness on multi-frequency designs and multiple FPGA devices

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Contact

• Pingakshya Goswami: pxg131330@utdallas.edu
• Dinesh Bhatia:

dinesh@utdallas.edu

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