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Chisel and FIRRTL for next-generation SoC designs

Jack Koenig�SiFive�CWG TAC Member

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Introduction�

What is the Chisel Working Group (CWG)?

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What is Chisel?

Constructing Hardware In a Scala Embedded Language
Domain Specific Language where the domain is digital design
NOT high-level synthesis (HLS) nor behavioral synthesis
Write Scala program to construct and connect hardware objects

Parameterized types
Object-Oriented Programming
Functional Programming
Static Typing w/ Powerful Type Inference

Intended for writing reusable hardware generators (libraries)

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No Loss of Expressibility: “Verilog-like” Chisel

FIR Filter - 3-point moving sum

What about >3 points?�What about weighted averages?

We want a generic FIR filter!

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Massive Increase in Parameterizability: “Software-like” Chisel

FIR Filter - Parameterized by bitwidth and coeffients with no loss of expressibility or performance.

Meta-programming enables powerful parameterization.

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Massive Increase in Parameterizability: “Software-like” Chisel

FIR Filter - Parameterized by bitwidth and coeffients with no loss of expressibility or performance.

Meta-programming enables powerful parameterization.

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Platform-Specific or Application-Specific RTL Changes

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IBM 45nm SOI

ST 28nm FDSOI

Zynq FPGA

Chip RTL

+ scan interface

+ snapshotting

+ interactive debug

+ clock-generators

+ SRAMs with init

+ specialized layout

+ SRAM macros

+ modified module hierarchy

+ specialized layout

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Realization: We need a software stack, but for hardware

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libraries

language

compiler

platforms

projects

x86

ARM

RISC-V

transforms

clang

Hwacha

Rocket

BOOM

rocketchip

chisel-utils

FIRRTL

Chisel Frontend

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FIRRTL: An Extensible Hardware Compiler Framework

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Modular Compiler Passes (Transforms)

Top

MyMux

...

Top

MyMux

...

Top

MyMux

...

Core

Transform

Custom

Transform

Metadata

Annotations

Metadata

Annotations

Metadata

Annotations

Robust Metadata/Annotations Support

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Projects of the Chisel Working Group

Chisel 3
FIRRTL
ChiselTest (formerly Chisel Testers 2)
Treadle
Chisel Bootcamp
Chisel Template

Chisel IOTesters
DSP Tools
Diagrammer

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Highlights

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Chisel v3.5.0 – v3.5.2 Released!

Lightning Highlights

Vec literal support
Scala 2.13 support (2.11 EOL)
Decoder + minimizer API in chisel3.util (w/ Espresso integration)
Source locator compacting
Many performance improvements

Chisel ~40-50% faster, FIRRTL ~20% faster

New Utilities – Gray code, scanLeftOr
RTL-IL backend

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See release notes on Github!

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Chisel v3.5.0 – v3.5.2 Released!

Lightning Highlights

Vec literal support
Scala 2.13 support (2.11 EOL)
Decoder + minimizer API in chisel3.util (w/ Espresso integration)
Source locator compacting
Many performance improvements

Chisel ~40-50% faster, FIRRTL ~20% faster

New Utilities – Gray code, scanLeftOr
RTL-IL backend

Digital Design with Chisel 3^rd ed. by Martin Schoeberl

https://www.imm.dtu.dk/~masca/chisel-book.html
Also in Chinese, Japanese, and Vietnamese!

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See release notes on Github!

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ChiselTest Improvements

Simpler peek/poke with Scala types
Improved Verilator simulation performance via JNA
Verilator backend now supports dumping FST instead of VCD
PeekPokeTester compatibility API

Helps migrate users off old chisel-iotesters

Simulation constructs can now be annotated
assert/assume/cover graduated out of experimental
Simulation binary caching
Support for bounded model checking (next slide)

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Native Formal Verification Support

Formal verification is assumed to be difficult for users
Good tooling and sensible defaults can help

Similar to simulator-based flow
Safe past function
Automatic reset guarding (default but disableable)

Close integration with simulation testing flow

Same basic APIs
Same IDE and tooling integration

Automatically runs counter examples through a simulator to provide a waveform
Native FIRRTL -> SMTLib or btor2 output
Works with Z3 and CVC4

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See Kevin Laeufer’s WOSET Paper https://woset-workshop.github.io/WOSET2021.html#article-3

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Native Formal Verification Support

Formal verification is assumed to be difficult for users
Good tooling and sensible defaults can help

Similar to simulator-based flow
Safe past function
Automatic reset guarding (default but disableable)

Close integration with simulation testing flow

Same basic APIs
Same IDE and tooling integration

Automatically runs counter examples through a simulator to provide a waveform
Native FIRRTL -> SMTLib or btor2 output
Works with Z3 and CVC4

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See Kevin Laeufer’s WOSET Paper https://woset-workshop.github.io/WOSET2021.html#article-3

This example verifies that when a Chisel memory with synchronous read port and WriteFirst behavior has a read and a write access to the same address, the new value will be returned. The check fails if WriteFirst is substituted with ReadFirst or Undefined (Section IV). It is based on a Verilog example from a popular blog. In the Chisel version, the assertion is automatically delayed until at least one cycle after reset, when there are valid past values available (Section VI). A bounded model check is executed by the verify command, which is called from a standard Scala unit test (Section III). When the check fails, the failing inputs and starting states are replayed on a simulator, resulting in a waveform file that is identical to the output we would get from a dynamic verification run. However, since we used bounded model checking to find the failing trace, it will be as short as possible. In our example, two cycles after reset are needed to fail the property. The first cycle contains the read and write requests and the second cycle observes the arbitrary result on the read port if we set the memory behavior to Undefined for read/write conflicts. The included screenshot was obtained with the open-source GTKWave waveform viewer.

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Definition / Instance

Historically, Chisel elaborates every module instance and then deduplicates structurally equivalent modules
New experimental API for definining (and elaborating) a module once and instantiating multiple times

Definition – Elaborates implementation of module
Instance – Merely instantiates public API

Major performance optimization for very large or hierarchical designs
Composes with cross-module reference annotations
Experimental – undergoing active development

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See https://www.chisel-lang.org/chisel3/docs/cookbooks/hierarchy.html for docs

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Definition / Instance

Historically, Chisel elaborates every module instance and then deduplicates structurally equivalent modules
New experimental API for definining (and elaborating) a module once and instantiating multiple times

Definition – Elaborates implementation of module
Instance – Merely instantiates public API

Major performance optimization for very large or hierarchical designs
Composes with cross-module reference annotations
Experimental – undergoing active development

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See https://www.chisel-lang.org/chisel3/docs/cookbooks/hierarchy.html for docs

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Definition / Instance

Historically, Chisel elaborates every module instance and then deduplicates structurally equivalent modules
New experimental API for definining (and elaborating) a module once and instantiating multiple times

Definition – Elaborates implementation of module
Instance – Merely instantiates public API

Major performance optimization for very large or hierarchical designs
Composes with cross-module reference annotations
Experimental – undergoing active development

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4/19/22

See https://www.chisel-lang.org/chisel3/docs/cookbooks/hierarchy.html for docs

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DataView

Often users want to manipulate hardware values as if they were a different type

AXI-style flat bus interface used as more structured hierarchy

Allows treating objects of one type as another
A superpowered union or cast, like View in SQL
Used to implement:

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See https://www.chisel-lang.org/chisel3/docs/explanations/dataview.html for docs

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DataView

Often users want to manipulate hardware values as if they were a different type

AXI-style flat bus interface used as more structured hierarchy

Allows treating objects of one type as another
A superpowered union or cast, like View in SQL
Used to implement:

Seamless integration with Scala types

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See https://www.chisel-lang.org/chisel3/docs/explanations/dataview.html for docs

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DataView

Often users want to manipulate hardware values as if they were a different type

AXI-style flat bus interface used as more structured hierarchy

Allows treating objects of one type as another
A superpowered union or cast, like View in SQL
Used to implement:

Seamless integration with Scala types
Bundle upcasting

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See https://www.chisel-lang.org/chisel3/docs/explanations/dataview.html for docs

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DataView

Often users want to manipulate hardware values as if they were a different type

AXI-style flat bus interface used as more structured hierarchy

Allows treating objects of one type as another
A superpowered union or cast, like View in SQL
Used to implement:

Seamless integration with Scala types
Bundle upcasting
User-defined mappings between types

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4/19/22

See https://www.chisel-lang.org/chisel3/docs/explanations/dataview.html for docs

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DataView

Often users want to manipulate hardware values as if they were a different type

AXI-style flat bus interface used as more structured hierarchy

Allows treating objects of one type as another
A superpowered union or cast, like View in SQL
Used to implement:

Seamless integration with Scala types
Bundle upcasting
User-defined mappings between types
Strip io_ prefix

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See https://www.chisel-lang.org/chisel3/docs/explanations/dataview.html for docs

New in 3.5.3

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Realization: We need a software stack, but for hardware

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4/19/22

libraries

language

compiler

platforms

projects

x86

ARM

RISC-V

transforms

clang

Hwacha

Rocket

BOOM

rocketchip

chisel-utils

FIRRTL

Chisel Frontend

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It is a lot of work to build and maintain a software stack

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libraries

language

compiler

platforms

projects

x86

ARM

RISC-V

transforms

clang

Hwacha

Rocket

BOOM

rocketchip

chisel-utils

FIRRTL

Chisel Frontend

Metadata /

Annotations

Custom

Infrastructure

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It is a lot of work to build and maintain a software stack

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libraries

language

compiler

platforms

projects

x86

ARM

RISC-V

transforms

clang

Hwacha

Rocket

BOOM

rocketchip

chisel-utils

FIRRTL

Chisel Frontend

Metadata /

Annotations

Shared

Infrastructure

Custom

Infrastructure

CIRCT

Multiple

Dialects

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What is MLIR?

“Multi-Level IR”
A generalization of LLVM

Part of the LLVM project

Infrastructure for building new compilers
Suitable for building new IRs
Can handle multiple IRs at once
Written in C++
Extremely performant

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CIRCT: Circuit IR for Compilers and Tools

What is CIRCT (pronounced “circuit”)?
An LLVM incubator project
Compiler infrastructure for generating Verilog
A collection of hardware dialects

FIRRTL Dialect
SystemVerilog Dialect*
RTL Dialects

Combinational
Sequential
Hardware

Timing Insensitive Dialects

Elastic Silicon Interconnect (ESI)
Handshake

A collection of tools for compiling circuits

e.g., firtool is a drop in replacement for firrtl

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What does this mean for Chisel?

Next generation FIRRTL compiler
Faster compilation (5-10x)
Less memory (5-10x)
Better Verilog emission
Robust platform for new features
Starting in Chisel 3.6

Built-in support for CIRCT

Starting in Chisel 3.7

Closer integration with CIRCT
CIRCT-first features

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7.6x

1.9x

4.3x

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Community

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Get Involved

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www.chisel-lang.org

Chat with us on Gitter

Ask questions on StackOverflow

Watch talks on YouTube

Also check out CIRCT

circt.llvm.org

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Extra / Old Slides

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AutoCloneType2

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cloneType is an implementation detail that leaks into the user API (since original Chisel)
Useless boilerplate
Original AutoCloneType works okay but has some limitations

Parameters must be defined as “vals”
Works in typical use cases but not all use cases
Slow

The Chisel compiler plugin now generates cloneType for all Bundles
Available in Chisel v3.4.3 (opt-in)

Improved in v3.4.4
Mandatory in v3.5.0

Before:

After:

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Further Improved Website

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Community page

www.chisel-lang.org

Now with a search bar!

Latest API Docs

Project-specific documentation

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Further Improved Website

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www.chisel-lang.org

Documentation examples are compiled and run!!!

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Enhanced Signal Naming (from last time)

Historically Chisel has struggled with signal naming
Chisel 3.4 has much better naming

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Old* Verilog

Chisel 3.4 Verilog

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Refined Signal Naming

Optional “tap” output
What should the name of the port be?

port
tap_port
tap
tapPort

In 3.4.0, the name was ”tap_port”
In 3.4.1 on, the name is “tap”
Additional improvements to naming (especially when using recursion)
Now with ~5 months of use, it’s going great!

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Improved Release Methodology

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major

Backport

major

Backport

3.2.x

master

3.3.x

3.3.0

3.2.1

3.2.0

Automated Backporting + CI

3.2-SNAPSHOT

3.3-SNAPSHOT

3.5-SNAPSHOT