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Basic I/O operations , stack and Encoding Machine instructions

COMPUTER ORGANIZATION

Prepared by

Mr. SUTHAGAR S/ AP/ ECE

Mr. SUTHAGAR S / AP/ ECE

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Basic Input/Output Operations

Mr. SUTHAGAR S / AP/ ECE

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Input/Output

  • The data on which the instructions operate are not necessarily already stored in memory.
  • Data need to be transferred between processor and outside world (disk, keyboard, etc.)
  • I/O operations are essential, the way they are performed can have a significant effect on the performance of the computer.

Mr. SUTHAGAR S / AP/ ECE

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Program-Controlled I/O Example

  • Read in character input from a keyboard and produce character output on a display screen.
  • Rate of data transfer (keyboard, display, processor)
  • Difference in speed between processor and I/O device creates the need for mechanisms to synchronize the transfer of data.
  • A solution: on output, the processor sends the first character and then waits for a signal from the display that the character has been received. It then sends the second character. Input is sent from the keyboard in a similar way.

Mr. SUTHAGAR S / AP/ ECE

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Program-Controlled I/O Example

- Registers

  • Flags

- Device interface

Mr. SUTHAGAR S / AP/ ECE

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Program-Controlled I/O Example

  • Machine instructions that can check the state of the status flags and transfer data:�READWAIT Branch to READWAIT if SIN = 0� Input from DATAIN to R1��WRITEWAIT Branch to WRITEWAIT if SOUT = 0� Output from R1 to DATAOUT

Mr. SUTHAGAR S / AP/ ECE

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Program-Controlled I/O Example

  • Memory-Mapped I/O – some memory address values are used to refer to peripheral device buffer registers. No special instructions are needed. Also use device status registers.��READWAIT Testbit #3, INSTATUS� Branch=0 READWAIT� MoveByte DATAIN, R1

Mr. SUTHAGAR S / AP/ ECE

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Program-Controlled I/O Example

  • Assumption – the initial state of SIN is 0 and the initial state of SOUT is 1.
  • Any drawback of this mechanism in terms of efficiency?
    • Two wait loops🡪processor execution time is wasted
  • Alternate solution?
    • Interrupt

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Stacks

Mr. SUTHAGAR S / AP/ ECE

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Home Work

  • For each Addressing modes mentioned before, state one example for each addressing mode stating the specific benefit for using such addressing mode for such an application.

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Mr. SUTHAGAR S / AP/ ECE

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Stack Organization

  • LIFO

Last In First Out

SP

Stack Bottom

Current�Top of Stack�TOS

0

1

2

3

4

7

8

9

10

5

6

Stack

0 0 5 5

0 0 0 8

0 0 2 5

0 0 1 5

0 1 2 3

FULL

EMPTY

Mr. SUTHAGAR S / AP/ ECE

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Stack Organization

  • PUSH

SP ← SP – 1

M[SP] ← DR

If (SP = 0) then (FULL ← 1)

EMPTY ← 0

SP

Stack Bottom

Current�Top of Stack�TOS

0

1

2

3

4

7

8

9

10

5

6

Stack

0 0 5 5

0 0 0 8

0 0 2 5

0 0 1 5

0 1 2 3

FULL

EMPTY

1 6 9 0

1 6 9 0

Current�Top of Stack�TOS

Mr. SUTHAGAR S / AP/ ECE

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Stack Organization

  • POP

DR ← M[SP]

SP ← SP + 1

If (SP = 11) then (EMPTY ← 1)

FULL ← 0

SP

Stack Bottom

Current�Top of Stack�TOS

0

1

2

3

4

7

8

9

10

5

6

Stack

0 0 5 5

0 0 0 8

0 0 2 5

0 0 1 5

0 1 2 3

FULL

EMPTY

1 6 9 0

1 6 9 0

Current�Top of Stack�TOS

Mr. SUTHAGAR S / AP/ ECE

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Stack Organization

  • Memory Stack
    • PUSH

SP ← SP – 1

M[SP] ← DR

    • POP

DR ← M[SP]

SP ← SP + 1

0

1

2

102

202

201

200

100

101

PC

AR

SP

Mr. SUTHAGAR S / AP/ ECE

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Additional Instructions

Mr. SUTHAGAR S / AP/ ECE

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Logical Shifts

  • Logical shift – shifting left (LShiftL) and shifting right (LShiftR)

C

R0

0

before:

after:

0

1

0

0

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1

.

.

.

1

1

0

0

1

1

1

0

0

0

(b) Logical shift r

ight

LShiftR #2,R0

(a) Logical shift left

LShiftL #2,R0

C

R0

0

before:

after:

0

1

0

0

0

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1

1

.

.

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1

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0

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.

.

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Arithmetic Shifts

C

before:

after:

0

1

1

1

0

0

0

1

.

.

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0

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1

1

0

0

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1

(c) Ar

ithmetic shift r

ight

AShiftR #2,R0

R0

.

.

.

Mr. SUTHAGAR S / AP/ ECE

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Rotate

Figure 2.32. Rotate instructions.

C

R0

before:

after:

0

1

0

0

0

1

1

1

.

.

.

1

1

1

0

1

1

1

0

0

1

(c) Rotate r

ight without carr

y

RotateR #2,R0

(a) Rotate left without carr

y

RotateL #2,R0

C

R0

before:

after:

0

1

0

0

0

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1

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0

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C

before:

after:

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1

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0

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0

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(d) Rotate r

ight with carr

y

RotateRC #2,R0

R0

.

.

.

.

.

.

(b) Rotate left with carr

y

RotateLC #2,R0

C

R0

before:

after:

0

1

0

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0

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0

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0

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1

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1

Mr. SUTHAGAR S / AP/ ECE

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Encoding of Machine Instructions

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Encoding of Machine Instructions

  • Assembly language program needs to be converted into machine instructions. (ADD = 0100 in ARM instruction set)
  • In the previous section, an assumption was made that all instructions are one word in length.
  • OP code: the type of operation to be performed and the type of operands used may be specified using an encoded binary pattern
  • Suppose 32-bit word length, 8-bit OP code (how many instructions can we have?), 16 registers in total (how many bits?), 3-bit addressing mode indicator.
  • Add R1, R2
  • Move 24(R0), R5
  • LshiftR #2, R0
  • Move #$3A, R1
  • Branch>0 LOOP

OP code

Source

Dest

Other info

8

7

7

10

(a) One-word instruction

Mr. SUTHAGAR S / AP/ ECE

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Encoding of Machine Instructions

  • What happens if we want to specify a memory operand using the Absolute addressing mode?
  • Move R2, LOC
  • 14-bit for LOC – insufficient
  • Solution – use two words

(b) Two-word instruction

Memory address/Immediate operand

OP code

Source

Dest

Other info

Mr. SUTHAGAR S / AP/ ECE

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Encoding of Machine Instructions

  • Then what if an instruction in which two operands can be specified using the Absolute addressing mode?
  • Move LOC1, LOC2
  • Solution – use two additional words
  • This approach results in instructions of variable length. Complex instructions can be implemented, closely resembling operations in high-level programming languages – Complex Instruction Set Computer (CISC)

Mr. SUTHAGAR S / AP/ ECE

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Encoding of Machine Instructions

  • If we insist that all instructions must fit into a single 32-bit word, it is not possible to provide a 32-bit address or a 32-bit immediate operand within the instruction.
  • It is still possible to define a highly functional instruction set, which makes extensive use of the processor registers.
  • Add R1, R2 ----- yes
  • Add LOC, R2 ----- no
  • Add (R3), R2 ----- yes

Mr. SUTHAGAR S / AP/ ECE