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Instructors

Dan Garcia and Bora Nikolic

inst.eecs.berkeley.edu/~cs61c �CS61C : Machine Structures�� Lecture 8 – Introduction to RISC-V�More Decisions; Logical; Procedures�

�

2018-09-10

Image source: Western Digital

Western Digital believes Big Data and Fast Data will need application-specific solutions and that RISC-V is ideal for delivering them (November 2017)

All Western Digital’s processor cores will be RISC-V �(>1 billion cores/year)!

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Review

Memory is byte-addressable, but lw and sw access one word at a time (one word is 4 bytes).
A pointer (used by lw and sw) is just a memory address, so we can add to it or subtract from it (using offset).
A Decision allows us to decide what to execute at run-time rather than compile-time.
C Decisions are made using conditional statements within if, while, do while, for.
RISC-V Decision making instructions are the conditional branches: beq and bne.
New Instructions:

lw, sw, lb, sb, lbu, beq, bne, blt, bltu, bge, j

CS61C L08 Introduction to RISC-V : Decisions, Procedures

Garcia, Nikolić, Fall 2018 © UCB

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Loops in C/Assembly

There are three types of loops in C:

while
do … while
for

Each can be rewritten as either of the other two, so the method used in the previous class can be applied to these loops as well.
Key Concept: Though there are multiple ways of writing a loop in RISC-V, the key to decision-making is conditional branch

CS61C L08 Introduction to RISC-V : Decisions, Procedures

Garcia, Nikolić, Fall 2018 © UCB

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RISC-V Logical Instructions

Logical operations	C operators	Java operators	RISC-V instructions
Bit-by-bit AND	&	&	and
Bit-by-bit OR	\|	\|	or
Bit-by-bit XOR	^	^	xor
Shift left logical	<<	<<	sll
Shift right logical	>>	>>	srl

Useful to operate on fields of bits within a word

e.g., characters within a word (8 bits)

Operations to pack /unpack bits into words
Called logical operations

CS61C L08 Introduction to RISC-V : Decisions, Procedures

Garcia, Nikolić, Fall 2018 © UCB

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RISC-V Logical Instructions

Always two variants

Register: and x5, x6, x7 # x5 = x6 & x7
Immediate: andi x5, x6, 3 # x5 = x6 & 3

Used for ‘masks’

andi with 0000 00FF_hex isolates the least significant byte
andi with FF00 0000_hex isolates the most significant byte

CS61C L08 Introduction to RISC-V : Decisions, Procedures

Garcia, Nikolić, Fall 2018 © UCB

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Your Turn. What is in x11?

xor x11,x10,x10

ori x11,x11,0xFF

andi x11,x11,0xF0

0x0
0xF
0xF0
0xFF00
0xFFFFFFFF

CS61C L08 Introduction to RISC-V : Decisions, Procedures

Garcia, Nikolić, Fall 2018 © UCB

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No NOT in RISC-V

There is no logical NOT in RISC-V

Use xor with 11111111_two
Remember - simplicity…

CS61C L08 Introduction to RISC-V : Decisions, Procedures

Garcia, Nikolić, Fall 2018 © UCB

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Logical Shifting

Shift Left Logical (sll) and immediate (slli): � slli x11,x12,2 #x11=x12<<2

Store in x11 the value from x12 shifted by 2 bits to the left (they fall off end), inserting 0’s on right; << in C.
Before: 0000 0002_hex�0000 0000 0000 0000 0000 0000 0000 0010_two
After: 0000 0008_hex�0000 0000 0000 0000 0000 0000 0000 1000_two
What arithmetic effect does shift left have?

Shift Right: srl is opposite shift; >>

CS61C L08 Introduction to RISC-V : Decisions, Procedures

Garcia, Nikolić, Fall 2018 © UCB

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Arithmetic Shifting

Shift right arithmetic (sra, srai) moves n bits to �the right (insert high-order sign bit into empty bits)
For example, if register x10 contained

1111 1111 1111 1111 1111 1111 1110 0111_two= -25_ten

If execute srai x10, x10, 4, result is:

1111 1111 1111 1111 1111 1111 1111 1110_two= -2_ten

Unfortunately, this is NOT same as dividing by 2ⁿ

Fails for odd negative numbers
C arithmetic semantics is that division should round towards 0

CS61C L08 Introduction to RISC-V : Decisions, Procedures

Garcia, Nikolić, Fall 2018 © UCB

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Your Turn. What is in x12?

x10 holds 0x34FF

slli x12,x10,0x10

srli x12,x12,0x08

and x12,x12,x10

0x0
0x3400
0x4F0
0xFF00
0x34FF

CS61C L08 Introduction to RISC-V : Decisions, Procedures

Garcia, Nikolić, Fall 2018 © UCB

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Helpful RISC-V Assembler Features

Symbolic register names

E.g., a0-a7 for argument registers (x10-x17)
E.g., zero for x0

Pseudo-instructions

Shorthand syntax for common assembly idioms
E.g., mv rd, rs = addi rd, rs, 0
E.g., li rd, 13 = addi rd, x0, 13

CS61C L08 Introduction to RISC-V : Decisions, Procedures

Garcia, Nikolić, Fall 2018 © UCB

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Administrivia

Quest is tonight!!!

You should have gotten an e-mail with seating assignment!
If you didn’t, contact us

CS61C L08 Introduction to RISC-V : Decisions, Procedures

Garcia, Nikolić, Fall 2018 © UCB

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Assembler to Machine Code (more later in course)

foo.S

bar.S

Assembler

foo.o

bar.o

Linker

lib.o

a.out

Assembler source files (text)

Machine code object files

Pre-built object file libraries

Machine code executable file

Assembler converts human-readable assembly code to instruction bit patterns

CS61C L08 Introduction to RISC-V : Decisions, Procedures

Garcia, Nikolić, Fall 2018 © UCB

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How Program is Stored

Memory

Bytes

Program

Data

One RISC-V Instruction = 32 bits

CS61C L08 Introduction to RISC-V : Decisions, Procedures

Garcia, Nikolić, Fall 2018 © UCB

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Program Execution

Processor

Control

Datapath

Registers

Arithmetic & Logic Unit

(ALU)

Memory

Bytes

Instruction

Address

Read Instruction Bits

Program

Data

PC (program counter) is internal register inside processor holding byte address of next instruction to be executed
Instruction is fetched from memory, then control unit executes instruction using datapath and memory system, and updates program counter (default is add +4 bytes to PC, to move to next sequential instruction; branches, jumps alter)

CS61C L08 Introduction to RISC-V : Decisions, Procedures

Garcia, Nikolić, Fall 2018 © UCB

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C Functions

main() {�int i,j,k,m;�...�i = mult(j,k); ... �m = mult(i,i); ...

}

/* really dumb mult function */

int mult (int mcand, int mlier){�int product = 0;�while (mlier > 0) {� product = product + mcand;� mlier = mlier -1; }�return product;�}

What information must�compiler/programmer �keep track of?

What instructions can

accomplish this?

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Six Fundamental Steps in Calling a Function

Put parameters in a place where function can access them
Transfer control to function
Acquire (local) storage resources needed for function
Perform desired task of the function
Put result value in a place where calling code can access it and restore any registers you used; release local storage
Return control to point of origin, since a function can be called from several points in a program

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RISC-V Function Call Conventions

Registers faster than memory, so use them
a0–a7 (x10-x17): eight argument registers to pass parameters and two return values (a0-a1)
ra: one return address register to return to the point of origin (x1)
Also s0-s1 (x8-x9) and s2-s11 (x18-x27): saved registers (more about those later)

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Instruction Support for Functions (1/4)

... sum(a,b);... /* a,b:s0,s1 */� }� int sum(int x, int y) {� return x+y;� }

address (shown in decimal)� 1000 � 1004 � 1008 � 1012 � 1016 � …� 2000 � 2004

RISC-V

In RISC-V, all instructions are 4 bytes, and stored in memory just like data. So here we show the addresses of where the programs are stored.

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Instruction Support for Functions (2/4)

... sum(a,b);... /* a,b:s0,s1 */� }� int sum(int x, int y) {� return x+y;� }

address (shown in decimal)� 1000 mv a0,s0 # x = a� 1004 mv a1,s1 # y = b � 1008 addi ra,zero,1016 #ra=1016� 1012 j sum #jump to sum� 1016 … # next instruction� …� 2000 sum: add a0,a0,a1� 2004 jr ra # new instr.“jump register”

RISC-V

CS61C L08 Introduction to RISC-V : Decisions, Procedures

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Instruction Support for Functions (3/4)

... sum(a,b);... /* a,b:s0,s1 */� }� int sum(int x, int y) {� return x+y;� }

2000 sum: add a0,a0,a1� 2004 jr ra # new instr. “jump register”

Question: Why use jr here? Why not use j?
Answer: sum might be called by many places, so we can’t return to a fixed place. The calling proc to sum must be able to say “return here” somehow.

RISC-V

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Instruction Support for Functions (4/4)

Single instruction to jump and save return address: jump and link (jal)
Before:� 1008 addi ra,zero,1016 #ra=1016� 1012 j sum #goto sum
After:� 1008 jal sum # ra=1012,goto sum
Why have a jal?

Make the common case fast: function calls very common
Reduce program size
Don’t have to know where code is in memory with jal!

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RISC-V Function Call Instructions

Invoke function: jump and link instruction (jal)

(really should be laj “link and jump”)

“link” means form an address or link that points to �calling site to allow function to return to proper address
Jumps to address and simultaneously saves the address of the following instruction in register ra

jal FunctionLabel

Return from function: jump register instruction (jr)

Unconditional jump to address specified in register: jr ra
Assembler shorthand: ret = jr ra

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“And in Conclusion…”

Registers we know so far (Most of them!)

a0-a7 for function arguments, a0-a1 for return values
ra return address
s0-s11 saved registers
zero

Instructions we know:

Arithmetic: add, addi, sub
Logical: sll, srl, sla, slli, srli, slai, and, or, xor, andi, ori, xori
Decision: beq, bne, blt, bge
Unconditional branches (jumps): j, jr
Functions called with jal, return with jr ra.

Start with an example next time

CS61C L08 Introduction to RISC-V : Decisions, Procedures