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MHS

SERVER

MHS'25 for Incubation Committee

These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

Approval Request

v1.0 Base Specs approved Q4’22, maintenance updates Q2’25.

Six Base Specifications Updates are available to sync up CD

1. FLW v1.0 RC5 -> v1.2 RC3 – Corey Hartman
2. SDNO v1.0 RC2 -> v1.1 RC1 – Michael Gregoire
3. DNO v1.0 RC5 -> v1.1 RC2 - Michael Gregoire
4. PIC v1.0 RC7 -> v1.11 RC1 – Cliff DuBay
5. XIO v1.0 RC4 -> v1.04 RC1 – Javier Lasa
6. PESTI v1.0 RC2-> v1.2 RC2- Javier Lasa

These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

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The MHS Mission

• What: Modular Hardware System

MHS envisions interoperability between key elements of datacenter, edge and enterprise infrastructure by providing consistent interfaces and form factors among modular building blocks.  

MHS standardizes a collection of HPM (Host Processor Modules) form-factors and supporting ingredients to allow interoperability of HPMs and platforms.

• Why
1. MHS aims to ultimately improve industry efficiency and innovation.
• Enable the CPU Suppliers to design and validate the circuit board under their CPUs
• While preserving the ability for the rest of the supply chain to innovate beyond the CPU
2. CPU Suppliers are enabled to innovate without barriers to adoption.
3. Platform Suppliers may innovate without burden of redesigning HPMs
• When: Shipping from multiple suppliers today!
• Who:

These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

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Contribution Hierarchy

Base Spec

Design Spec

Design Spec

Product Spec

Product Spec

Product Spec

Product Spec

MHS Contribution

These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

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Contribution Tenets

• Openness –MHS promotes open standards by defining interoperable hardware interfaces and form factors, enabling collaboration across vendors and reducing proprietary lock-in. All the Base Specifications are collaborations between multiple platform and silicon providers vs. contributions from singular companies.
• Efficiency – By using a modular approach, MHS provides accelerated TTM to large and small companies alike, component suppliers can now develop an ecosystem around MHS.
• Impact – The initiative drives industry-wide innovation by enabling faster deployment of new technologies and reducing the complexity of integrating diverse hardware systems.
• Scale – MHS supports scalable infrastructure by allowing modular upgrades and flexible configurations, which are essential for hyperscale and enterprise data centers.
• Sustainability - Through modularity and reuse of standardized components, MHS reduces electronic waste and supports longer hardware lifecycles (example chassis reuse), contributing to more sustainable IT practices.

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These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

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Full Width �Form Factor (FLW)�as part of DC-MHS Family

Corey Hartman

These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

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FLW v1.0 RC5 -> v1.2 RC3

• Updates for Alignment with OCP NIC trends
• Added Flexibility for cabled OCP NIC versions
• Added support for new OCP NIC form factor D-SFF (building upon Platform Custom zone)
• Moved OCP NIC LFF to Supplemental Info Section

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• Changed fixed location requirements on Power Egress connectors
• converted to recommended locations, with flexible zones
• to provide further flexibility in future designs

These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

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Scalable Density Optimized Form Factor (SDNO)�as part of DC-MHS Family

Mike Gregoire

These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

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M-SDNO v1.0 RC2 -> v1.1 RC1

• Support for 48V Power Ingress and Egress
• Aligned to M-PIC 1.1
• Consistent architecture with 12V
• Protection in place to avoid 12V / 48V incompatibility
• Support for CFF DC-SCM as an alternative to HFF DC-SCM
• Recommended Placement Zone
• Drive maximum consistency / compatibility
• Consistent for all Classes
• New HPM Class “E” which enables direct plug of M-CRPS power supplies into an M-SDNO HPM
• Chassis compatible with Class A and Class B

These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

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Density Optimized Form Factor (DNO)�as part of DC-MHS Family

Mike Gregoire

These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

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M-DNO v1.0 RC5 -> v1.1 RC2

• Completed Type 3 Definition
• Aligned length to SDNO defined 555mm

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• Various Updates for Consistency with SDNO
• OCP NIC Optional
• Updated strategy for mounting holes
• Added allowance for negative PCB features
• Re-Write of HSIO
• Updated HPM Assembly Thickness

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These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

Connect. Collaborate. Accelerate.

Platform Infrastructure Connectivity(M-PIC)�as part of the DC-MHS Family

Clifford DuBay

These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

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M-PIC v1.0 RC7 to v1.11 RC1

Previous Contribution content

• Defined common bidirectional 12V power delivery and management architecture to enable hardware between any HPM with any peripheral.
• Defined common 12V supply usage (Direct & PDB).
• Defined other common Platform Infrastructure & Connectivity (PIC) for hardware compatibility.

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New 48V Content

• Describes unidirectional, ramp-controlled distribution 48V power to all peripherals from Open Rack, M-CRPS, or other sources.
• Describes architectures that need to implement ramp control from 48V supplies ( ORv3 rack).
• Leverages 12V M-PIC distribution elements (connectors, pinouts, control) for the downstream, ramp-controlled 48V power.

Additional upgrades, clarifications, and corrections.

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These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

Connect. Collaborate. Accelerate.

M-PIC v1.0 RC7 to v1.11 RC1

Previous Contribution content Updates

• Added multiple clarifications, recommendations, and simplifications throughout.
• Updated document outline to improve readability and properly apply requirements.
• Updated PICPWR mating sequence and recommendations to avoid high-current in partial-mate conditions.
• Updated Blind-mate connector current rating.
• Improved compliance requirement visibility.
• Updated SFF-TA-1036 power rating.
• Converted PDB RFU pin to a power cycle/flex I/O pin.
• Enabled cabled boot use of PWRDIS functionality.
• Changed SB* topologies from 127kΩ to 100kΩ to increase margin.
• Added cable construction expectations for PDB and Control Pannel.
• Added requirements for configurations with more than one 12V_PRIMARY domain or 12VStby domain.

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48V (new) Additions

• Added 48V architectures and requirements for existing 12V HPMs with 12V peripherals and extending to 48V peripherals.
• Added 48V architectures and requirements for 48V HPMs and 48V peripherals.
• Added 48V SIF (Shared InFrastructure) architectures.
• Defined high level requirements for a new connectors.
• The M-PIC workstream reviewed Dedicated 48V Supply and 48V PICPWR design proposals from multiple vendors then selected a proposal for each. They design/product specification is expected to be contributed to OCP.
• M-PIC added an additional PDB Management connector with 6 additional pins to account for PDBs and HPMs that don’t connect PICPWR connectors between the PDB and the HPM.
• Defined consistent Ingress, egress, ramp control, and power enable/disable requirements.
• Define pass-through topologies for ramp-controlled supply connections to allow for design flexibility.

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These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

Connect. Collaborate. Accelerate.

eXtensible I/O �(M-XIO)

as part of the DC-MHS Family

Javier Lasa

These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

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M-XIO v1.0 RC4 to v1.04 RC1

Updates:

• Clarified 3P3AUX_MGMT rules.
• Added Chapter 4, specification compliance checklist.
• Added cabled expectations on SFF-TA-1016 to improve compatibility on chapter 8.
• Updated pull-up values on FLEXIO1, FLEXIO2 and CBL_PRES_A_PESTI_A_N from 127K to 100Kohms.

These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

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PEripheral Sideband Tunneling Interface (M-PESTI)

as part of DC-MHS Family

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Javier Lasa

These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

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M-PESTI v1.0 RC2 to v1.2 RC2

Editorial updates:

• Introduction was revised
• Re-ordered sections to describe required features before introducing optional
• features
• Updated several figures throughout the specification
• Clarified SPDM = Security Protocol & Data Model
• Removed reference to Example payload in section 8
• Clarified discovery status behavior during the active phase in section 8.1
• Re-ordered paragraphs in section 9 (Target Reset and Fault Handling)
• Replaced “shall” with “must” and “may” to “is permitted to”.

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Electrical updates:

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• BAUD accuracy tolerance changed to +/-2%.
• Revised Source to Destination discovery method.
• Pull-up resistor recommendation/example changed from 127K to 100K ohms (Figure 2,10).
• Simplified & Moved Discovery Status transition table (now table 3).
• Deleted “Express” Discovery Example (redundant).
• Changed “AFU” to “RSVD” to align to PCIe Spec language.
• Added simple presence pull down resistor range.
• Repaced static timing value with tDBREAK name in section 3.1.

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Logical updates to the specification:

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• Added PESTI fanout protocol details (New MSC command, tBPAUSE AC Timing parameter, and fanout rules).
• Simplified payload requirements. Format revision 01h and later governed by this specification.
• Corrected Endpoint Descriptor byte length of payload.
• Added MUX switch control response value definition.
• MUX fanout snooper rules have been added.
• Clarified CRC-8 exclusion statements during active phase.
• Modified fanout snooper rule to allow virtual wire exchange when no downstream channels are enabled.
• Fixed Section 11 (Security Considerations) header
• Added Discovery Bypass and Active Phase PEC Enable Initiator control registers.
• Modified Discovery rules with Discovery Bypass considered.
• Added optional Packet Error Checksum target support during Virtual Wire Exchange.
• Modified discovery payload format and bitfields to match PAYLOAD_FORMAT_VERSION = 02h defined in the PCI-SIG 6.2 specification.

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These meetings are recorded via audio and video. By participating you consent that these recordings may be made publicly available. Any presentation materials, proposals and meeting minutes are published on the respective project's wiki page and are open to the public in accordance with OCP's Bylaws and IP Policy. This can be found at http://opencompute.org/about/ocp-policies/.

Connect. Collaborate. Accelerate.

Questions

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