Power Dissipation

DR.P.SUVEETHA DHANASELVAM

DR.P.SUVEETHA DHANASELVAM

DR.P.SUVEETHA DHANASELVAM

DR.P.SUVEETHA DHANASELVAM

DR.P.SUVEETHA DHANASELVAM

Activity Factor

• Suppose the system clock frequency = f
• Let f_sw = αf, where α = activity factor
• If the signal is a clock, α = 1
• If the signal switches once per cycle, α = ½

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• Dynamic power:

DR.P.SUVEETHA DHANASELVAM

Power Dissipation Sources

• P_total = P_dynamic + P_static
• Dynamic power: P_dynamic = P_switching + P_shortcircuit
• Switching load capacitances
• Short-circuit current
• Static power: P_static = (I_sub + I_gate + I_junct + I_contention)V_DD
• Subthreshold leakage
• Gate leakage
• Junction leakage
• Contention current

DR.P.SUVEETHA DHANASELVAM

DR.P.SUVEETHA DHANASELVAM

DR.P.SUVEETHA DHANASELVAM

Dynamic Power Reduction

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• Try to minimize:
• Activity factor
• Capacitance
• Supply voltage
• Frequency

DR.P.SUVEETHA DHANASELVAM

DR.P.SUVEETHA DHANASELVAM

DR.P.SUVEETHA DHANASELVAM

Clock Gating

• The best way to reduce the activity is to turn off the clock to registers in unused blocks
• Saves clock activity (α = 1)
• Eliminates all switching activity in the block
• Requires determining if block will be used

DR.P.SUVEETHA DHANASELVAM

Capacitance

• Gate capacitance
• Fewer stages of logic
• Small gate sizes
• Wire capacitance
• Good floorplanning to keep communicating blocks close to each other
• Drive long wires with inverters or buffers rather than complex gates

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DR.P.SUVEETHA DHANASELVAM

Voltage / Frequency

• Run each block at the lowest possible voltage and frequency that meets performance requirements
• Voltage Domains
• Provide separate supplies to different blocks
• Level converters required when crossing

from low to high V_DD domains

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• Dynamic Voltage Scaling
• Adjust V_DD and f according to

workload

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DR.P.SUVEETHA DHANASELVAM

Static Power

• Static power is consumed even when chip is quiescent.
• Leakage draws power from nominally OFF devices
• Ratioed circuits burn power in fight between ON transistors

DR.P.SUVEETHA DHANASELVAM

Leakage Control

• Leakage and delay trade off
• Aim for low leakage in sleep and low delay in active mode
• To reduce leakage:
• Increase V_t: multiple V_t
• Use low V_t only in critical circuits
• Increase V_s: stack effect
• Input vector control in sleep
• Decrease V_b
• Reverse body bias in sleep
• Or forward body bias in active mode

DR.P.SUVEETHA DHANASELVAM

Gate Leakage

• Extremely strong function of t_ox and V_gs
• Negligible for older processes
• Approaches subthreshold leakage at 65 nm and below in some processes
• An order of magnitude less for pMOS than nMOS
• Control leakage in the process using t_ox > 10.5 Å
• High-k gate dielectrics help
• Some processes provide multiple t_ox
• e.g. thicker oxide for 3.3 V I/O transistors
• Control leakage in circuits by limiting V_DD

DR.P.SUVEETHA DHANASELVAM

Junction Leakage

• From reverse-biased p-n junctions
• Between diffusion and substrate or well
• Ordinary diode leakage is negligible
• Band-to-band tunneling (BTBT) can be significant
• Especially in high-V_t transistors where other leakage is small
• Worst at V_db = V_DD
• Gate-induced drain leakage (GIDL) exacerbates
• Worst for V_gd = -V_DD (or more negative)

DR.P.SUVEETHA DHANASELVAM

Power Gating

• Turn OFF power to blocks when they are idle to save leakage
• Use virtual V_DD (V_DDV)
• Gate outputs to prevent

invalid logic levels to next block

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• Voltage drop across sleep transistor degrades performance during normal operation
• Size the transistor wide enough to minimize impact
• Switching wide sleep transistor costs dynamic power
• Only justified when circuit sleeps long enough

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DR.P.SUVEETHA DHANASELVAM