CMSC 611: Advanced Computer Architecture

Tomasulo

Some material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slides

Some material adapted from Hennessy & Patterson / © 2003 Elsevier Science

Out of Order Execution

• Compiler rescheduling
• Static reordering based on latency
• Can’t span basic block
• Can only optimize for one branch direction
• CPU rescheduling
• CPU reads instructions in order
• Put instructions in a queue
• Start executing instructions out of order
• As resources and results are available

Tomasulo

• IF/ID fills queue of instructions
• Can go past branches, allowing FP operations beyond basic block in FP queue
• “Reservation Station” per execution unit
• Also for register result, load, store

Tomasulo Organization

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• The reservation stations hold instructions that had been issued and are awaiting execution at a functional unit
• All results from FP FU and loads are broadcasted on the CDB

Tomasulo Example

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Tomasulo Example Cycle 1

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Tomasulo Example Cycle 2

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Note: Can have multiple loads outstanding

Tomasulo Example Cycle 3

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• Note: registers names are removed (“renamed”) in Reservation Stations
• Load1 completing; what is waiting for Load1?

Tomasulo Example Cycle 4

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• Load2 completing; what is waiting for it?

Tomasulo Example Cycle 5

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Tomasulo Example Cycle 6

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Tomasulo Example Cycle 7

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• Add1 completing; what is waiting for it?

Tomasulo Example Cycle 8

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Tomasulo Example Cycle 9

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Tomasulo Example Cycle 10

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• Add2 completing; what is waiting for it?

Tomasulo Example Cycle 11

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Tomasulo Example Cycle 12

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• Note: all quick instructions complete already

Tomasulo Example Cycle 13

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Tomasulo Example Cycle 14

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Tomasulo Example Cycle 15

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• Mult1 completing; what is waiting for it?

Tomasulo Example Cycle 16

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• Note: Just waiting for divide

Tomasulo Example Cycle 55

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Tomasulo Example Cycle 56

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• Mult 2 completing; what is waiting for it?

Tomasulo Example Cycle 57

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• Again, in-order issue, out-of-order execution, completion

Tomasulo “Register Renaming”

• Operands to Functional Unit from Reservation Station, not registers
• Replaced by value or pointer to another reservation stations
• Don’t rely on the register name, avoids WAR, WAW hazards
• More reservation stations than registers
• Can do optimizations compilers cannot perform
• Results broadcast over Common Data Bus

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Reservation Station Components

• Functional Unit Reservation Station
• Op—Operation to perform in the unit (e.g., + or –)
• Vj, Vk—Value of Source operands
• Store buffers has V field, result to be stored
• Qj, Qk—Reservation stations producing source registers (value to be written)
• Store buffers only have Qi for RS producing result
• Busy—Indicates reservation station or FU is busy
• Register Reservation Station
• Register result status—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register.

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Three Stages of Tomasulo Algorithm

1. Issue—get instruction from FP Op Queue
• If reservation station free (no structural hazard), control issues instruction & sends operands (renames registers).
2. Execution—operate on operands (EX)
• When both operands ready then execute; if not ready, watch Common Data Bus for result
3. Write result—finish execution (WB)
• Write on Common Data Bus to all awaiting units; mark reservation station available

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Normal vs. Common Data Bus

• Normal data bus: data + destination
• (“go to” bus)
• Common data bus: data + source
• (“come from” bus)
• 64 bits of data + 4 bits of Functional Unit source address
• Write if matches expected Functional Unit (produces result)
• Broadcast: one to many

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Tomasulo Drawbacks

• Circuit complexity
• Many associative stores (CDB) at high speed
• Performance limited by Common Data Bus
• Multiple CDBs → more FU logic for parallel associative stores

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Tomasulo Loop Example

Loop: LD F0, 0(R1)

MULTD F4, F0, F2

SD F4, 0(R1)

SUBI R1, R1, #8

BNEZ R1, Loop

• Assume Multiply takes 4 clocks
• Assume first load takes 8 clocks (cache miss), second load takes 4 clocks (hit)
• To be clear, will show clocks for SUBI, BNEZ
• Reality, integer instructions ahead

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Loop Example Cycle 0

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Loop Example Cycle 1

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Loop Example Cycle 2

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Loop Example Cycle 3

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• Note: MULT1 has no registers names in RS

Loop Example Cycle 4

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• Issue SUBI

Loop Example Cycle 5

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• Issue BNEZ

Loop Example Cycle 6

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• Note: F0 never sees Load1 result

Loop Example Cycle 7

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• Note: MULT2 has no registers names in RS

Loop Example Cycle 8

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Loop Example Cycle 9

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• Load1 completing; what is waiting for it?

Loop Example Cycle 10

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• Load2 completing; what is waiting for it?

Loop Example Cycle 11

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Loop Example Cycle 12

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Loop Example Cycle 13

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Loop Example Cycle 14

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• Mult1 completing; what is waiting for it?

Loop Example Cycle 15

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• Mult2 completing; what is waiting for it?

Loop Example Cycle 16

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Loop Example Cycle 17

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Loop Example Cycle 18

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Loop Example Cycle 19

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Loop Example Cycle 20

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Loop Example Cycle 21

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Multiple Issue

• Static: Integer/FP instruction pairs
• Dynamic: Extend Tomasulo
• Must handle dependencies on issue
• Two instructions: split clock in half
• More: Explicit dependency issue logic

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Reorder Buffers

• Most modern processors use a variation of Tomasulo
• Add Reorder Buffer (ROB) in place of register stations & memory store
• Write from ROB in order issued
• Makes sure earlier instructions complete
• Simplifies exceptions & speculation

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ROB Changes

1. ROB holds:
• Destination (register or mem address)
• Slot for value (when done)
2. Other RS identified by ROB#
• Each RS knows what ROB# it is going to
• CDB b-cast: ROB1/value vs. Add2/value
3. Retire phase
• Check oldest ROB entries
• If done, “commit” write to reg or memory

Speculation with ROB

• Roll back PC
• Discard invalid ROB entries
• OK to leave everything else as-is
• Stuff in execution units can run, but nobody will be listening for the result on the CDB
• Exceptions happen at ROB retire