Blacksmith: Scalable Rowhammering �in the Frequency Domain

Patrick Jattke¹ Victor van der Veen² Pietro Frigo³ Stijn Gunter¹ Kaveh Razavi¹

¹ETH Zurich ²Qualcomm Inc. ³VU Amsterdam

43rd IEEE Symposium on Security & Privacy

May 23-26, 2022, San Francisco, CA

1

Summary

Samsung

Micron

Frequent Item Count Estimation

0

1

0

1

0

1

1

1

BLACKSMITH

100%

2

Background

a DRAM bank

Row buffer

a DRAM chip

• DRAM banks consist of rows and columns

3

Background

a DRAM bank

• DRAM banks consist of rows and columns

Row buffer

a DRAM chip

aggressor 2

victim

4

Rowhammer Attacks Are Practical

Network

ECC memory

Smartphone

Browser

Scenarios

DRAM Types

ECC

5

Methodology

Attack window

64 ms

6

Methodology

8192 intervals x 166 ACTs

= 1.3󠀠󠀠 M ACTs in total

Attack window

refresh interval (7.8 µs)

≈166 activations

​

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

7

Methodology

Example: Executing a 6-sided pattern

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

8

Methodology

Example: Executing a 6-sided pattern

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

9

Methodology

Example: Executing a 6-sided pattern

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

10

Methodology

Example: Executing a 6-sided pattern

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

Round

1

11

Methodology

Example: Executing a 6-sided pattern

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

Round

1

2

3

4

5

6

7

8

N-7

N-6

N-5

N-4

N-3

N-2

N-1

N

12

Methodology

Example: Executing a 6-sided pattern

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

Round

1

2

3

4

5

6

7

8

N-7

N-6

N-5

N-4

N-3

N-2

N-1

N

13

Methodology

Sampler

stream of DRAM ACT cmds

add(r_D)

Model of a mitigation

ACT(r_A)

ACT(r_D)

ACT(r_D)

ACT(r_C)

Normal operation

...

14

Methodology

Inhibitor

r_D

Model of a mitigation

Sampler

add(r_D)

stream of DRAM ACT cmds

At REFRESH time

TRR(r_D)

ACT(r_A)

ACT(r_D)

ACT(r_D)

ACT(r_C)

Normal operation

...

15

Methodology

Model of a mitigation

• Frequent item count estimation�is hard to solve in-DRAM

​

Sampler

add(r_d)

Inhibitor

r_D

stream of DRAM ACT cmds

ACT(r_A)

ACT(r_D)

ACT(r_D)

ACT(r_C)

Normal operation

...

At REFRESH time

TRR(r_D)

16

Methodology

DRAM is becoming more vulnerable

Manufacturing Year

Minimum�Rowhammer

Threshold

DDR4

DDR3

2012

2015

2018

2021

0

50k

100k

150k

17

Methodology

DRAM is becoming more vulnerable

Manufacturing Year

Minimum�Rowhammer

Threshold

DDR4

DDR3

2012

2015

2018

2021

0

50k

100k

150k

DRAM is becoming more vulnerable (lower R_th):�⇒ enables new attack patterns with less activations per aggressor

18

Methodology

​

Existing Rowhammer patterns

x+2

x+1

x

x-1

x-2

x-3

x-4

x-5

x-6

x-7

x+2

x+1

x

x-1

x-2

x-3

x-4

x-5

x-6

x-7

Single-sided

Double-sided

4-sided

x+2

x+1

x

x-1

x-2

x-3

x-4

x-5

x-6

x-7

19

Methodology

​

Existing Rowhammer patterns

x+2

x+1

x

x-1

x-2

x-3

x-4

x-5

x-6

x-7

x+2

x+1

x

x-1

x-2

x-3

x-4

x-5

x-6

x-7

x+2

x+1

x

x-1

x-2

x-3

x-4

x-5

x-6

x-7

Single-sided

Double-sided

4-sided

Access Frequency

Single-sided

Double-sided

4-sided

20

Methodology

​

Existing Rowhammer patterns

x+2

x+1

x

x-1

x-2

x-3

x-4

x-5

x-6

x-7

x+2

x+1

x

x-1

x-2

x-3

x-4

x-5

x-6

x-7

x+2

x+1

x

x-1

x-2

x-3

x-4

x-5

x-6

x-7

Single-sided

Double-sided

4-sided

Access Frequency

Single-sided

Double-sided

4-sided

💡Insight: All existing Rowhammer access patterns �hammer aggressors exclusively uniformly.

21

Methodology

​

Existing Rowhammer patterns

x+2

x+1

x

x-1

x-2

x-3

x-4

x-5

x-6

x-7

x+2

x+1

x

x-1

x-2

x-3

x-4

x-5

x-6

x-7

x+2

x+1

x

x-1

x-2

x-3

x-4

x-5

x-6

x-7

Single-sided

Double-sided

4-sided

Access Frequency

Single-sided

Double-sided

4-sided

💡Insight: All existing Rowhammer access patterns �hammer aggressors exclusively uniformly.

Can non-uniformity help to bypass Rowhammer mitigations?

22

Methodology

Exp. 1: n-sided patterns with non-uniformity

Introducing non-uniform aggressor accesses

r₁

r₃

r₅

r₇

r₉

r₁₁

r₁₃

r₁

r₃

r₅

r₇

r₉

r₁₁

r₁

r₃

r₅

r₇

r₉

r₁₁

r₁

r₃

r₅

r₇

r₉

r₁₁

r₁₅

r₁₃

r₁₅

Round 1

Round 2

Round 3

Round 4

…

random rounds

23

Methodology

Exp. 1: n-sided patterns with non-uniformity

Exp. 2: randomized patterns

Introducing non-uniform aggressor accesses

r₁

r₃

r₅

r₇

r₉

r₁₁

r₁₃

r₁

r₃

r₅

r₇

r₉

r₁₁

r₁

r₃

r₅

r₇

r₉

r₁₁

r₁

r₃

r₅

r₇

r₉

r₁₁

r₁₅

r₁₃

r₁₅

Round 1

Round 2

Round 3

Round 4

…

random rounds

Round 1

Round 2

Round 3

Round 4

…

random same-bank rows

random round

random pattern location

r₁

r₃

r₁

r₃

...

24

Methodology

20 x

10 x

6 x

4 x

Our DRAM Test Devices

Micron

Hynix

Samsung

Unknown�(Kingston)

Dec. ‘16

to Jun. ‘20

2132-2666 MHz

4–32

GiB

1-2

DRAM ranks

25

Methodology

Non-Uniformity Results

*Modules without any bit flips omitted

26

Methodology

Non-Uniformity Results

​

*Modules without any bit flips omitted

Modules where NON-UNIFORMITY is �needed to trigger bit flips

27

Methodology

Non-Uniformity Results

​

*Modules without any bit flips omitted

Modules where NON-UNIFORMITY is �needed to trigger bit flips

O1. Non-uniform aggressor accesses can lead to effective patterns on DIMMs where previous n-sided patterns could not trigger any bit flips.

28

Methodology

Non-Uniformity Results

​

*Modules without any bit flips omitted

Modules where UNIFORMITY is �needed to trigger bit flips

29

Methodology | DIMM A10

When should we hammer an aggressor?

REF

...

O2. Accessing aggressors at the “right” time in a pattern enables�to bypass the mitigation (sampler).

REF

⇒ no bit flips

r₁

r₃

r₁

r₃

⇒ no bit flips

⇒ no bit flips

⇒ no bit flips

⇒ no bit flips

⇒ bit flips!

⇒ no bit flips

access distinct random row

30

Methodology | DIMM A10

When should we hammer an aggressor?

...

REF

r₁

r₃

r₁

r₃

...

r₁

r₃

r₁

r₃

...

r₁

r₃

r₁

r₃

...

r₁

r₃

r₁

r₃

...

r₁

r₃

r₁

r₃

...

r₁

r₃

r₁

r₃

...

r₁

r₃

r₁

r₃

phase = 0

phase = 1

phase = 2

phase = 3

phase = 4

phase = 5

phase = 6

PHASE

0

1

2

3

4

5

6

7

31

Methodology | DIMM A10

​

For how long should we hammer an aggressor?

r₁

r₃

REF

r₁

r₃

REF

r₁

r₃

...

REF

...

...

r₁

r₃

...

...

...

r₁

r₃

r₁

r₃

...

...

32

Methodology | DIMM A10

​

For how long should we hammer an aggressor?

r₁

r₃

REF

r₁

r₃

REF

r₁

r₃

...

REF

r₁

r₃

...

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

...

r₁

r₃

...

r₁

r₃

...

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

...

...

...

⇒ no bit flips

⇒ bit flips!

⇒ more bit flips!

⇒ no bit flips

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₁

r₃

r₁

r₃

r₁

r₃

⇒ no bit flips

⇒ no bit flips

...

O3. Up to a sweet spot, increasing the hammering intensity leads to more bit flips. Then the number of bit flips drops.

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

...

⇒ no bit flips

...

...

...

33

Methodology | DIMM A10

​

For how long should we hammer an aggressor?

r₁

r₃

REF

r₁

r₃

REF

r₁

r₃

...

REF

r₁

r₃

...

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

...

amplitude = 1

amplitude = 2

amplitude = 3

AMPLITUDE

1x

2x

3x

34

Methodology | DIMM B2

​

Should our patterns be longer than one refresh interval?

r₁

r₃

REF

REF

r₁

r₃

REF

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

pattern length �= 2 REF intervals

r₁

r₃

r₁

r₃

r₁

r₃

r₁

r₃

...

r₁

r₃

r₁

r₃

...

...

r₁

r₃

r₁

r₃