Voltage Tunable Quantum Dots (VTQDs) for Realizing Quantum Superposition in Complementary-Metal-Oxide- Semiconductor (CMOS) structures
Sanatan Chattopadhyay
Quantum Materials, Devices and Digital Microfluidics Group (QMat & DigiMF)
Department of Electronic Science
University of Calcutta
Topics of discussion
Introduction
Introduction: the domain
MOSFET: basic unit of Systems
MOSFET: basic unit of Systems
Constraints:
Bit Line
Word Line
DRAM
VDD
n-MOS
p-MOS
Symbol
Market
80% dominated by CMOS
97% covered by Si
SRAM
Physics of MOSFETs
VD = 0
VG = 0
VD = VDS
p-substrate
n-substrate
N++
P++
P++
N++
EC
EV
EC
EV
EC
EV
EC
EV
Quantum Superposition Principle
Qubit
|ψA〉 = α|0〉 + β|1〉
|ψA〉 = cos(θ/2)|0〉 + sin(θ/2)eiφ|1〉
Quantum Gate Operations
Basic Gates
NOT
σx =
0 1
1 0
|0〉 ↔ |1〉
Phase
σz =
1 0
0 -1
|0〉 → |0〉
|1〉 → -|1〉
Hadamard
H =
1 1
1 -1
|0〉 → |0〉 + |1〉
|1〉 → |0〉 - |1〉
Gate
Matrix
Result
Qubit Implementation
Device
Information
|0〉
|1〉
Challenge
Photonic
Polarization
Horizontal
Vertical
Scalability
Absorption/
scattering
No. of photons in Fock state
Vacuum
1-photon
Arrival time
Early
Late
Super-conducting
Josephson junction
Charge
One extra Cooper pair
No extra Cooper pair
Flux/
Current
Counter-clockwise
Clockwise
Phase/
Energy
1st excited state
Ground state
QD
Up
Down
Dot spin
Double-QD
Electron on Right dot
Electron on Left dot
Electron localization
T ~ mK
Coherence time low
T ~ mK
T ~ mK
Advantage
Room Temp
operation
Fidelity 99.4%
No. of entangled qubit high
Semiconductor
Charge Based
Fidelity 99%
Trapped ion
Lower Hyperfine level
Energy level
Upper Hyperfine level
Fidelity 99.9%
Coherence time very high
Laser require-ment
Topology
Emerging (claimed to be braids)
Anyons
?
Coherence
Challenges
Why Quantum Dots (QDs) ?
Important effects of size quantization:
Applications of QDs
Source: Science; August 6; 2021; Semiconductor quantum dots: Technological progress and future challenges
Migration to quantum ‘components’
Requirement: QDs in room temperature
Quantum dots should fulfill the following requirements to make them useful for devices at room temperature:
Size
For a band offset of 0.3 eV, QD diameter ~ 4 nm.
Maximum limit
E2 and E1 are the 2nd and 1st energy states.
For GaAs/AlGaAs QDs: ~ 12 nm; InAs/AlGaAs QDs: ~ 20 nm.
ΔEc: conduction band offset.
ΔEc
Materials, Devices and Technology at Quantum scale
Quantum Dot (QD) technology
- CVD
- MOCVD
- MBE
CdS
Molten Silicate
AlGaAs
GaAs
AlGaAs
Top - Down
InAs
GaAs
As2
In
GaAs
Bottom - Up
D. Bimberg, M. Grundmann, N. Ledenstov, “Quantum Dot Heterostructures”
Deposition
Lithography
Etching
Top down
CVD
Self assembled atoms / molecules
Bottom up
Synthesis of QDs by following wet chemical route
(Self assembled atoms / molecules)
Exciton
h+
e
Hole
rexciton
e
H - atom
Wannier-Mott exciton
(mimicking the H-atom in solid state)
e-
h+
h+
h+
h+
h+
e-
e-
e-
e-
Electron
Positively charged hole
Exciton
(electron-hole pair)
Excitation of an electron from the VB to CB producing an exciton
(e- is in CB and h+ residing in VB)
Illustration of Exciton in semiconductor
Exciton
The energy values of the exciton are the solutions to the particle in a box with the mass replaced by reduced mass.
R=radius of a spherical particle; m* = corresponding effective mass;
Exciton
The exciton binding energy due to Coulomb attraction between the negatively charged electron and positively charged hole is given by the following relationships (in analogy with those of H-atom where is to be replaced by reduced mass):
For H-atom?
Excitonic Bohr Radius
The equation of Bohr radius of H-atom is given by (in SI unit):
The Bohr radius of exciton in a semiconductor is the natural separation distance between the hole (in VB) and electron (CB) and it is a characteristics property of that semiconductor. It is given by:
Excitonic Bohr Radius
Excitonic Bohr radius of:
GaAs:
CdSe:
Quantum scale materials
Semiconductor | SI | GaAs | CdSe | CdS | ZnSe |
Eg (eV) | 1.27 | 1.52 | 1.84 | 2.58 | 2.82 |
Rexciton | 4.3 | 11.3 | 4.9 | 2.8 | 3.8 |
Bulk
EC
EV
Realization of quantum effects in MOS devices
Distribution of charges with voltage
P-Substrate
Back contact
Oxide
Gate
Accumulation
VG < 0
+++++++++++
P-Substrate
Back contact
Oxide
Gate
Inversion
VG >> 0
- - - - - - - - - - -
P-Substrate
Back contact
Oxide
Gate
Depletion
VG > 0
-
-
-
-
-
-
Holes are attracted
Holes are repelled
Electrons are attracted
Accumulation
Depletion
Inversion
Band diagram in MOS
Metal
SiO2
Semiconductor
φm
φsi
Ec
EV
EFP
Ei
χsi
χsiO2
Metal
SiO2
P-type
Vg < 0
When the band bends downward, ψs> 0; and when it bends upward, ψs< 0.
Band bending and Surface potential
Metal
SiO2
P-type
Vg > 0
Depth from surface
inversion charge
depletion charge
Inversion
Depletion
Ψs
P-Si
Depletion
SiO2
Bulk
Metal
Surface quantization in MOS
Inversion
Ψs
Surface quantization
Depth
Carrier profile
Charge centroid
Voltage Tunable Quantum Dots
(VTQDs)
MOS based QD (VTQD)
Nanowire MOS based VTQD
Approach for analytical modeling
Nanowire/QD Hamiltonian
(Second quantization Field operator )
Isolated Energy Eigenvalues/Eigenstates
Arbitrary potential profile
Real Space
Mode Space
Utilization of quantum property to improve computational efficiency
Self-Energy Calculation
Non-Equillibrium Green’s Function (NEGF) Formalism
LDOS
Charge Distribution
Poisson’s Equation
Calculated Potential
Potential Profile
Transmission coefficient
Current
Capacitance
Self-consistency check
Strain Incorporation
Contact Modeling
Coupling with Reservoir
Coupling with Photons
Coupling with Phonons
J Appl Phys. 115 (12), 124502 2014); 125 (8), 082506(2019), Sup. Latt. Micro. Struct. 97, 548-555 (2016); Trans. Elect. Dev. 65 (2), 411-418 (2016); J. Comp. Elect. 18 (2), 465 (2019), Phys. Rev. Appl. 15(2), 024055 (2021), 15 (5), 054060 (2021).
Schematic representation of VTQD formation
Fabrication of VTQD array
Optimizing EBL-parameters for fabrication
PMMA concentration, PMMA-layer thickness, Pre-bake time, Write field, Operating voltage, Operating distance, Magnification, System aperture, Electron dose, Developer and stopper solution concentration and time, Post-bake time.
Substrate
PMMA-layer
e-beam exposure
‘Low Dose’
‘Optimum Dose’
‘High Dose’
e-beam exposure
e-beam exposure
Substrate
PMMA-layer
PMMA
layer
Substrate
Electron
backscattering
Fabrication process steps
Fabricated vertical Pt/SiO2/Ge-nanowire MOS
R = 28 nm
R = 25 nm
Fabricated vertical NWMOS device: contd…
70kµC/cm2; 250nm spacing
60kµC/cm2; 150nm spacing
50kµC/cm2; 150nm spacing
Fabricated vertical NWMOS device: contd…
Room Temperature Confinement
S. Chattopadhyay et al.; Physical Review Applied, 2021.
A proposed MOSFET based Qubit
Possible MOSFET based Qubit
Operational at Room Temp.
Superposition and Measurement
S. Chattopadhyay et al., Advanced Quantum Technologies 6, 2200072 (2023).
Qubit Gate Operation
(VG1, VG2) = (1.15, 1.30) V
|0〉
ΔVG2 = 46 mV
|1〉
NOT
ΔVG2 = 42 mV
Hadamard
(|0〉+|1〉)
1
√2
Initialization
@ |1〉, VG1, can be varied to change the phase between states, until the 1st excited state is occupied.
Bloch Sphere
ΔVG2 = (30 + 2) mV
Qubit Read-out
Rabi oscillation
Stability diagram
(0,0)
(1,0)
(0,1)
(1,1)
Patterned nanowire FET @CRNN
Patterned nanowire FET @CRNN
Summary
Acknowledgement
Laboratories:
THANK YOU!