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Voltage Tunable Quantum Dots (VTQDs) for Realizing Quantum Superposition in Complementary-Metal-Oxide- Semiconductor (CMOS) structures

Sanatan Chattopadhyay

Quantum Materials, Devices and Digital Microfluidics Group (QMat & DigiMF)

Department of Electronic Science

University of Calcutta

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Topics of discussion

  • Few introductory statements (MOS devices).
  • Semiconductor quantum structures.
  • MOS devices and surface quantization.
  • Concept of voltage tunable quantum dots (VTQDs).
  • Fabrication of quantum dot devices.
  • Quantum superposition in quantum- /nano- wire FETs.
  • Summary.

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Introduction

  • Realization and implementation of quantum theory is perhaps the most valuable contributions in physics in the last 100 years.
  • This invaluable discovery has enabled the creation of multiple branches of modern physics.
  • The most fascinating essence of quantum theory is that it is implementable in almost all the material systems.
  • The modern buzz of quantum computing, quantum information processing, quantum communication and quantum cryptography, is also the gift from quantum theory.

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Introduction: the domain

  • Quantum computing, quantum information processing, quantum communication and quantum cryptography are the invaluable gifts of the progress of quantum theory.
  • The basic unit is qubit and such scalable Qubits operate only at very low temperature (~ mK).
  • The emerging device schemes for qubit generation are different from the state-of-the-art classical bits, and these are not compatible with the CMOS technology.
  • Presently 97% of the electronics market is dominated by CMOS technology.
  • Continuous scaling of MOSFETs since 1970’s has resulted in the emergence of NW-/QW FETs.
  • Currently, TSMC, Intel and Samsung are manufacturing NW/QW- FETs of 3 nm technology node.

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MOSFET: basic unit of Systems

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MOSFET: basic unit of Systems

Constraints:

  • Power.
  • Speed.
  • Size.

Bit Line

Word Line

DRAM

VDD

  • Data volume: Tera-bits (TB).
  • Numerous functionalities.

n-MOS

p-MOS

Symbol

Market

80% dominated by CMOS

97% covered by Si

SRAM

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Physics of MOSFETs

VD = 0

VG = 0

VD = VDS

p-substrate

n-substrate

N++

P++

P++

N++

EC

EV

EC

EV

EC

EV

EC

EV

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Quantum Superposition Principle

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Qubit

  • Weightage of the two states, i.e., |α|2 and |β|2 are the probability to get either |0〉 or |1〉 on read-out.
  • Weightage of the two states and the phase difference, i.e., φ, can be manipulated by gate operations.
  • It can be represented by Bloch sphere.

A〉 = α|0〉 + β|1〉

A〉 = cos(θ/2)|0〉 + sin(θ/2)e|1〉

  • Any quantum system is a superposition of two orthogonal states, i.e., |0〉 and |1〉, is a qubit.

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Quantum Gate Operations

Basic Gates

NOT

σx =

0 1

1 0

|0〉 ↔ |1〉

Phase

σz =

1 0

0 -1

|0〉 → |0〉

|1〉 → -|1〉

Hadamard

H =

1 1

1 -1

|0〉 → |0〉 + |1〉

|1〉 → |0〉 - |1〉

Gate

Matrix

Result

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Qubit Implementation

Device

Information

|0〉

|1〉

Challenge

Photonic

Polarization

Horizontal

Vertical

Scalability

Absorption/

scattering

No. of photons in Fock state

Vacuum

1-photon

Arrival time

Early

Late

Super-conducting

Josephson junction

Charge

One extra Cooper pair

No extra Cooper pair

Flux/

Current

Counter-clockwise

Clockwise

Phase/

Energy

1st excited state

Ground state

QD

Up

Down

Dot spin

Double-QD

Electron on Right dot

Electron on Left dot

Electron localization

T ~ mK

Coherence time low

T ~ mK

T ~ mK

Advantage

Room Temp

operation

Fidelity 99.4%

No. of entangled qubit high

Semiconductor

Charge Based

Fidelity 99%

Trapped ion

Lower Hyperfine level

Energy level

Upper Hyperfine level

Fidelity 99.9%

Coherence time very high

Laser require-ment

Topology

Emerging (claimed to be braids)

Anyons

?

Coherence

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Challenges

  • The conceptual areas with relevant theories have progressed significantly.
  • The area of quantum algorithm has also been developed.
  • Data transmission with quantum communication protocol finds good progress.
  • However, the technological implementation at room temperature has not been affordable yet.
  • Very difficult to communicate with the people working in different sections of these areas.
  • Should have an appropriate way to exchange ideas and their possible physical implementations.

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Why Quantum Dots (QDs) ?

  • Quantum confinement (QC) of electrons and holes.
  • Formation of quantized and discrete electronic energy levels.
  • Energy gap (ΔE) between the successive energy levels increases as the size of the nanomaterial decreases as in a ‘particle in a box’ model.
  • The energy level spacing in the nanomaterial is greater than the thermal energy as in atom (ΔE > kBT).

Important effects of size quantization:

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Applications of QDs

Source: Science; August 6; 2021; Semiconductor quantum dots: Technological progress and future challenges

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Migration to quantum ‘components’

  • Enormous progress have been made in the computer technology.
  • The no. of atoms needed to represent a bit in memory has been decreasing exponentially since 1950.
  • Similarly, the no. of transistors per chip, clock speed, and energy dissipation per logic operation have also exhibited exponential improving trend.
  • However, such rate of improvement is not sustainable any more after the year 2020 since one bit of information will require only few/ one atom (s) to represent it.
  • The problem is that the behavior of a computer’s components will be dominated by the principles of quantum physics at this size.

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Requirement: QDs in room temperature

Quantum dots should fulfill the following requirements to make them useful for devices at room temperature:

  1. Sufficiently deep localizing potential and small QD size.
  2. QD ensembles should show high uniformity.
  3. Material should be coherent, i.e., defect free.

 

Size

For a band offset of 0.3 eV, QD diameter ~ 4 nm.

Maximum limit

 

E2 and E1 are the 2nd and 1st energy states.

For GaAs/AlGaAs QDs: ~ 12 nm; InAs/AlGaAs QDs: ~ 20 nm.

ΔEc: conduction band offset.

ΔEc

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Materials, Devices and Technology at Quantum scale

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Quantum Dot (QD) technology

  • Epitaxial growth / deposition:

- CVD

- MOCVD

- MBE

CdS

Molten Silicate

AlGaAs

GaAs

AlGaAs

Top - Down

InAs

GaAs

As2

In

GaAs

Bottom - Up

D. Bimberg, M. Grundmann, N. Ledenstov, “Quantum Dot Heterostructures”

Deposition

Lithography

Etching

Top down

CVD

Self assembled atoms / molecules

Bottom up

Synthesis of QDs by following wet chemical route

(Self assembled atoms / molecules)

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Exciton

  • When an electron excited from the VB to CB through the absorption of incident photon energy, it creates a hole in the VB. The electron-hole pair (excited electron in CB and hole in the VB) is called the exciton.
  • Such electron-hole pair may be considered to constitute a hydrogen- like atom in solid state.
  • The effective mass approximation in semiconductor allows to neglect the periodic crystal potential and considers the electrons and holes as free particles.
  • The wave functions and their energy values can be obtained by solving the Schrodinger equation analogous to the one describing the electron state in a hydrogen atom.

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h+

e

Hole

rexciton

e

H - atom

Wannier-Mott exciton

(mimicking the H-atom in solid state)

e-

h+

h+

h+

h+

h+

e-

e-

e-

e-

Electron

Positively charged hole

Exciton

(electron-hole pair)

Excitation of an electron from the VB to CB producing an exciton

(e- is in CB and h+ residing in VB)

Illustration of Exciton in semiconductor

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Exciton

The energy values of the exciton are the solutions to the particle in a box with the mass replaced by reduced mass.

R=radius of a spherical particle; m* = corresponding effective mass;

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Exciton

The exciton binding energy due to Coulomb attraction between the negatively charged electron and positively charged hole is given by the following relationships (in analogy with those of H-atom where is to be replaced by reduced mass):

For H-atom?

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Excitonic Bohr Radius

The equation of Bohr radius of H-atom is given by (in SI unit):

The Bohr radius of exciton in a semiconductor is the natural separation distance between the hole (in VB) and electron (CB) and it is a characteristics property of that semiconductor. It is given by:

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Excitonic Bohr Radius

Excitonic Bohr radius of:

GaAs:

CdSe:

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Quantum scale materials

Semiconductor

SI

GaAs

CdSe

CdS

ZnSe

Eg (eV)

1.27

1.52

1.84

2.58

2.82

Rexciton

4.3

11.3

4.9

2.8

3.8

  • Comparison of Bang gap and Exciton Bohr radius of few semiconductors:

Bulk

EC

EV

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Realization of quantum effects in MOS devices

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Distribution of charges with voltage

P-Substrate

Back contact

Oxide

Gate

Accumulation

VG < 0

+++++++++++

P-Substrate

Back contact

Oxide

Gate

Inversion

VG >> 0

- - - - - - - - - - -

P-Substrate

Back contact

Oxide

Gate

Depletion

VG > 0

-

-

-

-

-

-

Holes are attracted

Holes are repelled

Electrons are attracted

Accumulation

Depletion

Inversion

  • Charge distributions depend on the applied voltage and frequency of the applied ac signal.

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Band diagram in MOS

Metal

SiO2

Semiconductor

φm

φsi

Ec

EV

EFP

Ei

χsi

χsiO2

Metal

SiO2

P-type

Vg < 0

  • For ψs<0, accumulation of holes (band bends upward) for p-type substrate.
  • For ψs > 0, accumulation of electrons for n-type substrate.

When the band bends downward, ψs> 0; and when it bends upward, ψs< 0.

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Band bending and Surface potential

Metal

SiO2

P-type

Vg > 0

Depth from surface

inversion charge

depletion charge

Inversion

Depletion

Ψs

P-Si

Depletion

SiO2

Bulk

Metal

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Surface quantization in MOS

Inversion

Ψs

  • Inversion layer forms within 5 to 7 nm of the interface.

Surface quantization

Depth

Carrier profile

Charge centroid

  • Surface quantization effect modifies transport properties in the MOS devices significantly.
  • Surface quantization effect can be exploited for developing novel optoelectronic and quantum devices.
  • Carriers do not gather exactly @ interface.
  • The carriers’ peak appears at a certain depth from the interface.

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Voltage Tunable Quantum Dots

(VTQDs)

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MOS based QD (VTQD)

Nanowire MOS based VTQD

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Approach for analytical modeling

Nanowire/QD Hamiltonian

(Second quantization Field operator )

Isolated Energy Eigenvalues/Eigenstates

Arbitrary potential profile

Real Space

Mode Space

Utilization of quantum property to improve computational efficiency

Self-Energy Calculation

Non-Equillibrium Green’s Function (NEGF) Formalism

LDOS

Charge Distribution

Poisson’s Equation

Calculated Potential

Potential Profile

Transmission coefficient

Current

Capacitance

Self-consistency check

Strain Incorporation

Contact Modeling

Coupling with Reservoir

Coupling with Photons

Coupling with Phonons

J Appl Phys. 115 (12), 124502 2014); 125 (8), 082506(2019), Sup. Latt. Micro. Struct. 97, 548-555 (2016); Trans. Elect. Dev. 65 (2), 411-418 (2016); J. Comp. Elect. 18 (2), 465 (2019), Phys. Rev. Appl. 15(2), 024055 (2021), 15 (5), 054060 (2021).

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Schematic representation of VTQD formation

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Fabrication of VTQD array

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Optimizing EBL-parameters for fabrication

  • Optimization process:
  • Optimizing parameters:

PMMA concentration, PMMA-layer thickness, Pre-bake time, Write field, Operating voltage, Operating distance, Magnification, System aperture, Electron dose, Developer and stopper solution concentration and time, Post-bake time.

Substrate

PMMA-layer

e-beam exposure

Low Dose

Optimum Dose

High Dose

e-beam exposure

e-beam exposure

Substrate

PMMA-layer

PMMA

layer

Substrate

Electron

backscattering

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Fabrication process steps

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Fabricated vertical Pt/SiO2/Ge-nanowire MOS

  • FESEM images are taken at 120 kX magnification and 3 kV operating voltage with electron dose of 65k µC/cm2.

R = 28 nm

R = 25 nm

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Fabricated vertical NWMOS device: contd…

70kµC/cm2; 250nm spacing

60kµC/cm2; 150nm spacing

50kµC/cm2; 150nm spacing

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Fabricated vertical NWMOS device: contd…

  • TEM image of single nanowire MOS device showing different regions.
  • Obtained Nanowire-radius ~25 nm & oxide thickness ~20 nm.
  • Showing formation of Ge [400]-plane at 2θ = 62.60 on [400]-plane of Si substrate.
  • SAED spots arranged in ring like pattern, attributed to [400]-plane of Ge.

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Room Temperature Confinement

S. Chattopadhyay et al.; Physical Review Applied, 2021.

  • Indicates the formation of voltage tunable Quantum Dot.
  • In inversion, as per calculation, three quantum states are created within 2.5 V bias.
  • Thus, 6 electrons are confined in the these states.
  • The electron states and electron numbers can be engineered!!

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A proposed MOSFET based Qubit

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Possible MOSFET based Qubit

  • A ballistic dual-gate NW-FET (<10 nm) on SOI substrate.
  • Gate voltages create VTQDs within Nanowire with quantized/ discrete energy levels.
  • Choose materials with low effective mass (e.g., GaAs ~0.06, InP ~0.08, Ge ~0.08).
  • Energy spacing of quantum states in VTQDs ~ 500 meV (>> KTRoom/q); the effects of phonon scattering is negligible at Room Temperature.
  • Gate voltages manipulate the superposition along with phase.
  • Small drain bias is applied for read-out.

Operational at Room Temp.

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Superposition and Measurement

S. Chattopadhyay et al., Advanced Quantum Technologies 6, 2200072 (2023).

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Qubit Gate Operation

(VG1, VG2) = (1.15, 1.30) V

|0〉

ΔVG2 = 46 mV

|1〉

NOT

ΔVG2 = 42 mV

Hadamard

(|0〉+|1〉)

1

√2

Initialization

@ |1〉, VG1, can be varied to change the phase between states, until the 1st excited state is occupied.

Bloch Sphere

ΔVG2 = (30 + 2) mV

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Qubit Read-out

Rabi oscillation

Stability diagram

  • Pulse repetition time (lifetime of electron pulse entering QD-1) ~336.5 ns.
  • Qubit oscillation frequency ~25 MHz.
  • Characteristic decay time for qubit dephasing ~73 ns.

(0,0)

(1,0)

(0,1)

(1,1)

  • Inter-QD resonance tunneling splits single state into ‘bonding’ and ‘anti-bonding’ states.
  • Relevant gate voltages lead to either of the states (0,0), (1,0), (0,1), (1,1).
  • Curvature of the ‘bonding’ and ‘anti-bonding’ states depend on strength of inter-dot coupling.

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Patterned nanowire FET @CRNN

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Patterned nanowire FET @CRNN

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Summary

  • Quantum Dots can be realized in MOS structures.
  • Voltage tunable quantum dots (VTQDs) are appropriate for controlling the carrier confinement level.
  • It shows the potential for room temperature electron confinement.
  • VTQDs can be engineered to realize quantum superposition, leading to qubit generation near room temperature
  • Such VTQDs are solely implementable in the mainstream CMOS platform.

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Acknowledgement

  • Mr. Debopam Bhattacharya
  • Mr. Sandip Bhattacharya
  • Mr. Subrata Mondal
  • Mr. Susoman Dey
  • Ms. Ankita Sengupta
  • Mr. Bodhisatwa Roy
  • Ms. Aindrila Roy

Laboratories:

  • QMat & DigiMF Device Group (Quantum Scale Materials, Devices & Digital Microfluidics Research Group).
  • Center for Research in Nanoscience and Nanotechnology (CRNN), CU.
  • Center of Excellence (COE): System Biology and Biomedical Engineering, CU.
  • Dr. Basudev Nag Chowdhuty
  • Dr. Subhrajit Sikdar
  • Dr. Anupam Karmakar
  • Dr. Chirantan Das
  • Dr. Ananya Bhattacharya
  • Dr. Rajib Saha
  • Dr. Subhadip Chakraborty
  • Dr. Jenifer Sultana
  • Dr. Somdatta Paul
  • Dr. Anindita Das
  • Dr. Mainak Palit
  • Dr. Abhisek Das
  • Dr. Kunal Sinha
  • Dr. Sayan Kanungo
  • Dr. Sulagna Chatterjee

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THANK YOU!