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Registers

&

Bus System

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What is a register?
What is Register Transfer Language (RTL)?
How computer implements decisions?
What is a bus?
How to design a bus system to transfer data from one register to another?

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Basic Computer Organization and Design: Instruction Codes, Computer Registers, Computer Instructions, Timing and Control, Instruction Cycle, Memory-Reference Instructions, Input Output and Interrupt, Complete Computer Description, Design of Basic Computer.

Micro programmed Control: Control Memory, Address Sequencing, Micro program Example, Design of Control Unit

Unit-2

What you’ll learn

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Register

A hardware device that stores binary data such as

Address and Data for program execution
E.g., Program Counter (PC) and Instruction Register (IR)

(a) Register R1

(b) Showing individual bits

(c) Number of bits

(d) Divided into two parts

3

R1

7 6 5 4 3 2 1 0

R2

15 0

15 8

7 0

PC(H)

PC(L)

Register representation

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Computer Hardware

Internal Organisation specifies

Set of registers it contains and their function.
The sequence of microoperations performed on the binary information stored in the registers.
The control that initiates the sequence of microoperations.

Internal organisation of a system and logic circuits needed for its design are described using Register Transfer Language (RTL)

RTL is the symbolic notation used to describe microoperation transfers among registers.

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Register Transfer Notation (RTN)

Used to describe the transfer of information from one location to another.

Possible locations are memory locations, processor registers, or I/O registers.
Location is identified by a symbolic name standing for its hardware binary address.

Examples

Memory locations’ addresses: LOC, PLACE, A, VAR2.
Processor register names: R0, R5.
I/O register names: DATAIN, OUTSTATUS.

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Expression

The right hand side always denotes a value, and the left hand side is the name of a location where the value is to be placed, overwriting the old contents.

R2←R1

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Memory Read

Transfer of information from a memory word to the outside environment

Memory Write

Transfer of new information to be stored into the memory

M[AR]←R1

DR←M[AR]

Memory to Register

The contents of memory location LOC are transferred into register R1

Register Addition

Adds the contents of registers R1 and R2, and places their sum into R3

R3←[R1]+[R2]

R1←[LOC]

R3←R1+R2

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Transfer from R1 to R2 when P=1

Conditional Expression

7

R2

Clock

R1

/ n

P

Load

Control Unit

t

t+1

Transfer occurs here

Clock

Load

☞The control function is a boolean variable that is equal to 1 or 0.

☞The control condition is terminated with a colon.

P: R2←R1 [If (P=1) then (R2←R1)]

(The transfer is executed only when P=1)

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Sequential Circuits

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Combinatorial Circuit

Flip-flops

Inputs

Clock

Outputs

Sequential circuit

It is dependent on clock cycles
Depends on present as well as past inputs to generate any output.

Combinatorial Circuit

Output depends only upon present input.

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How a Computer Implements Decisions

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Operation

IF (a=b) THEN do this ELSE do that

Two actions are necessary

Data operation involving the comparison of a and b
Control action that selects between one of two courses of action

The THEN code
The ELSE code

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Implementation

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Decision Circuit

Comparator

A

B

Data inputs to be compared

Result of comparison

2 X 1

MUX

0

1

Current address (ELSE address/ Address path on not equal)

Next address

Branch address (THEN address/ Address path on equal)

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Bus

Computers contain a number of buses that provide pathways between components

Shared transmission media connecting 2 or more devices together
Broadcast, 1 to all operation
Must ensure only one device places information onto a bus at any given time

Typical Buses (50-100 lines)

Address information (address bus)

Specifies source/ destination of data transfer
Width determines the capacity of the system

Data information (data bus)

Width is key in determining overall performance

Control information – controls access to and use of the address and data bus
Miscellaneous – power, ground, clock

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Bus Performance

Data propagation delay through the bus – longer buses (to support more devices) require longer delays
Aggregate demand for access to the bus from all devices connected to the bus

To avoid bottlenecks, multiple buses are used

High speed limited access buses close to the processor
Slower speed general access buses farther away from the processor

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Bus Arbitration

Process of insuring only one device places information onto the bus at a time

Master – slave mechanism

Master is given control of the bus and can place information onto it. Slave receives the information.

Centralized

Central controller mediates all requests for the bus.

Decentralized

No centralized controller. All devices contain logic to control access to the bus.

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Bus Timing

Synchronous [e.g., PCI bus]

Occurrence of bus events is determined by the clock
All events start at the beginning of a clock cycle

Asynchronous [e.g., Futurebus⁺]

The occurrence of one event follows and depends on the occurrence of a previous event
More flexible and complicated than synchronous bus
Accommodates wider range of device speeds

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Registers Connected to Common Bus

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Reg. A

common bus

S1

S5

Reg. B

S2

S6

Reg. C

S3

S7

Reg. D

S4

S8

Source:

Reg.A

[Close Switch S1]

Destination:

Reg.C

[Close Switch S7]

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Bus System for Two Registers

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2 X 1

MUX 1

0

1

Reg. B

2 - line common bus

0

1

S

2 X 1

MUX 0

0

1

Reg. A

0

1

S	Reg.
0	A
1	B

1 X 2

Decoder

S

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Three State Buffer

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Normal Input A

Control Input C

Output Y=A if C=1

High impedance if C=0

A

Bus line

B

1 X 2

Decoder

S

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Recap

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Video Links

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