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Unit 4�Sequential Logic Circuit

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S-R flip flop

  • The circuit output response to the S & R inputs only at the +ve edges of clock pulse at any other instance of time. The SR flip flop will not response to the changes in the input
  • The truth table for SR flip flop as follows
    1. Case 1: S =R= 0 and the clock pulse is applied the output do not change i.e Qn+1= Qn
    2. Case 2: S =0 and R= 1 and the clock pulse is applied, Qn+1 = 0. The flip flop is reset
    3. Case 3: S =1 and R= 0 and the clock pulse is applied, Qn+1 = 1. The flip flop is set
    4. Case 4: S =R= 1 and the clock pulse is applied, the state of the flip flop is undefined

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S-R flip flop Timing Diagram

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Drawback of SR Flip Flop

  • When S and R input of the SR flip flop are logic 1 the state of the flip flop is undefined
  • When the power is turn on the state of the flip flop is uncertain

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Clocked S-R flip flop

  • When P = C = 1 the circuit, the circuit operates in accordance with the truth table of SR flip flop
  • When P= 1 and C = 0, the flip flop is reset
  • When P= 0 and C = 1, the flip flop is set

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JK Flip Flop

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JK Flip Flop

The operation of JK flip flop

  • The operation of JK flip flop is as follows
    1. Case 1: J = K = 0 and the output does not change
    2. Case 2: J = 1 and K = 0 makes Q = 1 i.e. set state
    3. Case 3: J = 0 and K = 1 makes Q = 0 i.e. reset state
    4. Case 4: J = K = 1, it toggles the flip flop output

Race Around Condition

  • In JK Flip-flop, if J=K=1, and if clk = 1 for a long period of time, then Q output will toggle as long as CLK is high, which makes the output of the flip-flop unstable or uncertain.
  • This problem is called race around condition in J-K flip-flop.
  • This problem (Race Around Condition) can be avoided by ensuring that the clock input is at logic “1” only for a very short time. This introduced the concept of Master Slave JK flip flop.

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Master Slave JK flip flop

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Master Slave JK flip flop

  • The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in a series configuration. Out of these, one acts as the “master” and the other as a “slave”.
  • In addition to these two flip-flops, the circuit also includes an inverter. The inverter is connected to clock pulse in such a way that the inverted clock pulse is given to the slave flip-flop.
  • In other words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and if CP=1 for master flip flop then it becomes 0 for slave flip flop.
  • If J=0 and K=1, thus the slave copies the master.
  • If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the Negative transition of the clock sets the slave, copying the master.
  • If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on the negative transition of the clock.
  • If J=0 and K=0, the flip flop is disabled and Q remains unchanged.

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D Flip Flop

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D Flip Flop Timing Diagram

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Timing Diagram of T Flip Flop

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Difference between Asynchronous and Synchronous Counters

Asynchronous

Synchronous

In this type of counter flip flop are connected in such a way that output of first flip flop connected to the clock of next flip flop

In this type of counter there is no connection between output of first flip flop and the clock of next flip flop

All the flip flops are not clocked simultaneously

All the flip flops are clocked simultaneously

Logic circuit is very simple

Logic circuit is complex

Draw is their low speed

They have high speed

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Difference between Asynchronous and Synchronous Counters

Ripple Counter: Ripple counter is an Asynchronous counter. It got its name because the clock pulse ripples through the circuit. An n-MOD ripple counter contains n number of flip-flops and the circuit can count up to 2n  values before it resets itself to the initial value.

These counters can count in different ways based on their circuitry.

UP COUNTER: Counts the values in ascending order.�DOWN COUNTER: Counts the values in descending order.�UP-DOWN COUNTER: A counter which can count values either in the forward direction or reverse direction is called an up-down counter or reversible counter.�DIVIDE by N COUNTER: Instead of a binary, we may sometimes require to count up to N which is of base 10. Ripple counter which can count up to value N which is not a power of 2 is called Divide by N counter.

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4 bit ripple/ Asynchronous up counter

Circuit Diagram

Timing Diagram

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Truth Table

Count

Output

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Q A

QB

QC

QD

0

0

0

0

0

1

1

0

0

0

2

0

1

0

0

3

1

1

0

0

4

0

0

1

0

5

1

0

1

0

6

0

1

1

0

7

1

1

1

0

8

0

0

0

1

9

1

0

0

1

10

0

1

0

1

11

1

1

0

1

12

0

0

1

1

13

1

0

1

1

14

0

1

1

1

15

1

1

1

1

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4 bit Ripple/Asynchronous Down Counter

Circuit Diagram

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Ripple/Asynchronous Up/Down Counter

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Truth table for Ripple/Asynchronous Up/Down Counter

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4 bit Serial in Parallel Out

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4 bit Serial in Parallel Out

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4 bit Serial in Serial Out

You may think what’s the point of a SISO shift register if the output data is exactly the same as the input data. Well this type of Shift Register also acts as a temporary storage device or it can act as a time delay device for the data, with the amount of time delay being controlled by the number of stages in the register, 4, 8, 16 etc or by varying the application of the clock pulses. Commonly available IC’s include the 74HC595 8-bit Serial-in to Serial-out Shift Register all with 3-state outputs.

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Shift Registers

  • A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for each data bit.
  • The output from each flip-Flop is connected to the D input of the flip-flop at its right.
  • Shift registers hold the data in their memory which is moved or “shifted” to their required positions on each clock pulse.
  • Each clock pulse shifts the contents of the register one bit position to either the left or the right.
  • The data bits can be loaded one bit at a time in a series input (SI) configuration or be loaded simultaneously in a parallel configuration (PI).
  • Data may be removed from the register one bit at a time for a series output (SO) or removed all at the same time from a parallel output (PO).
  • One application of shift registers is in the conversion of data between serial and parallel, or parallel to serial.
  • Shift registers are identified individually as SIPO, SISO, PISO, PIPO, or as a Universal Shift Register with all the functions combined within a single device.

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Shift Registers

  • Serial-in Parallel-out (SIPO)  -  the register is loaded with serial data, one bit at a time, with the stored data being available at the output in parallel form.
  • Serial-in Serial-out (SISO)  -  the data is shifted serially “IN” and “OUT” of the register, one bit at a time in either a left or right direction under clock control.
  • Parallel-in Serial-out (PISO)  -  the parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control.
  • Parallel-in Parallel-out (PIPO)  -  the parallel data is loaded simultaneously into the register, and transferred together to their respective outputs by the same clock pulse.
  • Universal Shift Register – (MUX)

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4 bit Parallel in Parallel Out

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4 Bit Parallel In Serial Out

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Universal Shift Register