Advanced PCB Engineering

Lecture 6:

Advanced Digital Layout and Via Management

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University of California, Berkeley

IEEE Student Branch

University of California, Berkeley

IEEE Student Branch

Logistics

• Attendance on bCourses
• Assignments due:
• Reminder: Lab checkoffs have in-person component and bCourses submission!
• Lab 4 in-person checkoff form + bCourses submission
• Project Layout! → bCourses submission (Simulation in addition to layout!) linked on bCourses (due 3/17, 11:59p)
• This week’s lab: High Speed Digital Design and Simulation (due 3/17, 11:59p)
• Links & Forms:
• OH GCal ← add to your calendar!
• Anon Feedback
• Extension Requests

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When is it Digital Design?

• When transferring and storing data/information as 1’s and 0’s
• Circuits that aide that goal are called Digital Circuits
• It is
• Data busses
• MCU’s
• FPGA’s
• Logic Circuitry

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Single Ended vs Differential vs OD/OC

• Single ended - Single wire bus for data - SPI, UART
• Simplest wiring and layout, but very subject to noise
• Open Drain/Open Collector - IC only pulls low, floats otherwise (or pulls up) - I2C
• Deterministic wire state, easier to debug, but slow
• Differential - Transmit both inverted and normal signal on two wires, HI and LOW - CAN, RS485
• Better in noisy environments, less signal error, but complex wiring and layout

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Single-Ended vs Differential Routing

Differential Pairs: two tracks routed in parallel carrying a data signal and its inversion to suppress common mode noise that would affect a high speed signal

Each trace in the pair should have a specific impedance, that impedance enables a certain speed of signal to be transmitted across the diff pair

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Manhattan Routing

• The most important style of routing when ground layers aren’t split
• Switch horizontal to vertical between layers to prevent coupling

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Clock Trace Routing

• Clocks usually operate at high frequencies, the following are steps to avoid noise on a clock line:
• Keep clock traces as straight as possible. Use 45-degree traces instead of right-angle bends.
• Do not use multiple signal layers for clock signals.
• Do not use vias in clock transmission lines. Vias can cause impedance change and reflection.
• Place a ground plane next to the outer layer to minimize noise. If you use an inner layer to route the clock trace, sandwich the layer between reference planes.
• Terminate clock signals to minimize reflection.
• Use point-to-point clock traces as much as possible.
• Separate clock traces from any nearby traces by 3*(Trace Width)

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Clock Routing Style

We want to divide our clock out to all peripherals without adding excessive loops so we use the Star-Routing style

If we have BGA IC’s using the clock, we can use daisy chain routing

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Impedance Profiles

• We want to ensure all of our high -speed traces have the desired impedance
• Would be very hard to measure/guess the board capacitance, inductance and resistance manually
• Altium allows you to setup up a impedance profile for each desired impedance/high speed bus

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Setting a Net Class or Trace Impedance Profile

• We can use the Design Rules to have our ActiveRouter automatically use a impedance profile we defined for the routing widths of traces

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Differential Impedance Profiles

• Similar to single ended, but notice our differential pair gap is now also defined

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Under ‘Type’, we can set Differential/Single

Specify the impedance in ‘Target Impedance’

Specify the precision in ‘Target Tolerance’

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Microstrip vs Stripline Impedance

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Bad Diff Routing

Why?

• Routes like this break the differential profile designed by Altium, leading to noisy, or mistimed signals

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Good Diff Routing

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Length Tuning

• To ensure all signals in a bus arrive at the same time (clock edge), we add winding routes to traces to match the overall length of trace segments

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Length Variation Formula

First, we need the propagation of our signal, while c is a good approximation, this is dependent on you dielectric, generally c/2 is used

From there we can get trace length delay from allowable time delay

For time delay, depends on signal, but generally can use 10% of period

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Length Match Example

Let’s consider an example where we need to determine the trace length required to achieve a time delay of 1 nanosecond, given a PCB material with a dielectric constant of 4.

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FR-4 tends to actually have a Dk of 4.2-4.5

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SPI Clocking Walkthrough

• If you would like to see where these timing delay requirements come from, check out this walkthrough with the SPI interface
• adcs-spi-communications-timing-presentation.pdf

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How to Length Tune

• Length tuning should happen between data traces in the same high speed bus

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What if I have series resistors or AC caps in the bus?

• You still want to match total bus length, x1+x2

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Length Tuning Shapes

• Each shape can benefit certain routing scenarios, depends on the size of area available and how much spacing between traces is required
• Generally we use accordion as it is the easiest to route and the densest

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Sizing Tuning Loops

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Spacing Tuning Loops

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Minimize Crosstalk and Loops

Bad

Bad

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How Do You Length Match This Bus?

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• For all buses, keep the same track profile for each trace in the bus
• Same length on each layer
• Same number of layer changes
• Layer changes all go to the same layer

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Why is it important for all data lines in a high speed bus to change the same number of layer and to the same layer

• Switching layers adds length, and different layers have different impedance profiles, and therefore different signal speeds ie on outer layers signals are faster than on internal layers

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Strategic Via Placement to Prevent Crosstalk

Bad

Good

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BGA Routing

Intel Application Note

common practice to place the largest BGA component first and use it to start floorplanning the PCB layout

1. Signal layer count: Determining the number of signal layers needed in the stackup will influence the number of plane layers, as well the resulting trace width needed to route into the design.
2. Fanout: How will signals enter and exit the BGA? Is controlled impedance needed? These questions will determine the layer count in the stackup, which will then determine how traces will be routed in the inner layers.

Two escape/fanout methods: dogbone(for larger pitch BGAs) or via-in-pad(for small pitch or impedance controlled BGAs)

The easiest way to manage the power connections into a BGA is to use power rails, typically on one or two plane layers.

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Why BGA?

Fewer damaged leads—BGA leads consist of solid solder balls, which are less likely to suffer damage during handling.

More leads per unit area

Smaller footprints—BGA packages are usually 20% to 50% smaller than QFP packages

Integrated circuit speed advantages—BGA packages operate well into the microwave frequency spectrum and achieve high electrical performance by using ground planes, ground rings, and power rings in the package construction.

Improved heat dissipation—Because the die is located at the center of the BGA package and most GND and VCC pins are located at the center of the package, the GND and VCC pins are located under the die.

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BGA-driven Layer Stackup

• Two outermost rows on one layer (Always layer of chip)
• At least 1 power and 1 GND layers, sometimes 2-2
• After that, most BGAs can do 2 rows per layer
• If there is extra space due to pin removal, can fit more rows per layer

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Via-in-pad Design

Application Note

For via-in-pad, always make sure the via is smaller than the pad itself around 90-75% of pad size is ok

Make sure you don’t tent vias-in-pad or your pads will be covered with solder mask

Vias-in-pad need to be conductive so we will fill with resin or copper and cap with a pad to ensure solder doesn’t drip into the via

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Via Types

• Depending on board density and size, you may need to switch via types, remember smaller vias have higher parasitic inductance and resistance, but lower parasitic capacitance
• Like the board you want to balance these parasitics

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Return Paths

• To minimize noise and reflections we want our signal traces to be short, but the return path must also be short

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Board Stack-ups for High Speed

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Preventing Crosstalk

• Widen spacing between signal lines as much as routing restrictions will allow. Try not to bring traces closer than three times the dielectric height.
• Design the transmission line so that the conductor is as close to the ground plane as possible.
• Use differential routing techniques where possible, especially for critical nets (i.e., match the lengths as well as the gyrations that each trace goes through).
• If there is significant coupling, route single-ended signals on different layers orthogonal to each other

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Parasitics

• Generally, you’ll find that the parasitic inductance in various places in your board is on the order of nH, while parasitic capacitance reaches on the order of pF
• Bandlimiting: Parasitic/stray capacitance acts like a low-pass filter, which creates rolloff in a transmission line transfer function or components like resistors.
• Coupling: In general, this refers to the ability for a signal to pass from one conductor to another unintentionally. For example, capacitive coupling creates crosstalk between traces.
• Impedance modification: This is related to bandlimiting and coupling. Stray/parasitic capacitance will modify impedance by producing a displacement current in nearby conductors.

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Parasitic Inductance

When working with any components that switch quickly, especially switching power supplies, the momentary burst of current from the switching component and the propagating signal along a trace will induce a voltage spike in a nearby trace. A trace with a larger parasitic inductance will experience a larger induced voltage spike. This generally increases bit error rates in digital systems, although in power electronics, this can cause involuntary switching in nearby logic circuits.

Reducing parasitic inductance requires making the equivalent loop area covered by traces as small as possible. The best way to do this is to place the ground plane for critical traces directly above the layer containing your ground plane. (Minimize Ground Loop)

While making layers in your layer stack thinner will decrease the loop area and the parasitic inductance, it will increase parasitic capacitance. Therefore, you need the sweet spot where inductance is minimized and capacitance is minimized

Resistors exhibit parasitic inductance at high frequencies, which can distort signal integrity:

• Use surface-mount resistors (SMT) instead of through-hole resistors to reduce parasitic inductance.

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Parasitic Resistance

Choose Inductors with low ESR

Short wide traces

Have enough solder on connections, but not too much

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Questions?

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Lab Time

• Lab 4: High Power Schematic Design
• Extension Form: http://berkie.ee/ape-sp25-extension
• Comments? Fill out the feedback form at: http://berkie.ee/ape-sp25-anon-feedback

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University of California, Berkeley

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