1 of 73

EE 198: Hands-On PCB Engineering

Lecture 1: Introduction

Password: Layers

University of California, Berkeley

IEEE Student Branch

University of California, Berkeley

IEEE Student Branch

2 of 73

Before all else.. Installing KiCad

  • Download the latest stable release of KiCad (9.0.4) or log into the Lab Computers using your Calnet ID!
  • https://www.kicad.org/download/

We heavily recommend using KiCad with a mouse!

(And using Git for version control)

University of California, Berkeley

IEEE Student Branch

3 of 73

Introduction

All you need to pretend you read the syllabus.

  • Kicad - Install it
  • Welcome!
  • Course Staff Introduction
  • All Kinds of Logistics
  • Jumping right in.. What even is this PCB thing I signed up for?

University of California, Berkeley

IEEE Student Branch

4 of 73

Welcome!

You are now and forever officially a HOPE bestie.

  • Fourteenth (!!!) offering: Fall 2025
  • Brought to you by:
    • The IEEE Student Branch at UC Berkeley
      • Check out at https://ieee.berkeley.edu/ !
    • Apple Inc.
    • Bay Area Circuits
    • JLCPCB
    • Digikey
  • ..And an awesome team of ~20 staff!

Years�of HOPE-ing

cope-ing

University of California, Berkeley

IEEE Student Branch

5 of 73

Course Staff:

Find many of us in OH (posted soon)

Charles Paxson

5th Year MS MechEng

Ansh Thakkar

2nd Year EECS

Ishaan Gupta

4th Year Mech Eng

+ EECS

Janus Sucharitakul

2nd Year EECS

Ailsa Sun �3rd Year Math

Inez Alvarez

Alek Norman 3rd Year EECS

Stephen Terry

3rd Year EECS

Aarav Singh

3rd Year EECS

Anthony Miceli

3rd Year EECS

Nathan Chang

3rd Year EECS

Curtis Manascsa

3rd Year EECS

John Lomax

5th Year MS EECS

APE Director

Carolyn Sun

3rd Year EECS + Physics

Noah Nizamian�3rd Year EECS

Rick Huang

EECS Super Senior

Nandini Velinedi�4th Year EECS

Roman Silivra

2nd Year EECS

Sai Praneth K

3rd Year Astrophysics + CS

Olivia Phongsa

3rd Year EECS

University of California, Berkeley

IEEE Student Branch

6 of 73

Logistics

  • EE 198-002/4
  • 2 Unit P/NP (6 hours / week)
    • Average 2 hours outside of class for labs, due after a week
    • More project work toward the latter half of the course
    • Warning to students not coming from an EE background
  • Wednesday/Thursday 8-10pm, Cory 125 (Bear Walk)
  • https://hope.berkie.ee*
  • When enrolled, you should be added to the class bCourses/Edstem*
    • most waitlisted and auditors will get limited access.

University of California, Berkeley

IEEE Student Branch

7 of 73

Enrollment Logistics

Enrollment codes have been sent out via email.

  • Apologizes for the email spam

Waitlisted folks - please don’t forget to fill out attendance!

  • We will use it to distribute extra codes.

If you are a Concurrent Enrollment student, we have to prioritize Matriculated students (but we will try put you on the waitlist).

Switching sections? Waiting for people to drop? Unit cap questions?

Ask now!

University of California, Berkeley

IEEE Student Branch

8 of 73

Support Logistics

  • Student Support efforts!
    • DSP requests? Life struggles? We’re even MORE here for you!!
  • Make a private post on Ed!
  • Extension Policy: All students will have a maximum of three (3) extensions granted for any reason: File for them at http://berkie.ee/hope-fa25-extension
    • 1 week for lab assignments, 1 day for project deadlines EXCEPT FINAL SUBMISSION AND DESIGN REVIEWS
  • If you have three unexcused absences and missed checkoffs we will reach out to you concerning participation in this class. (But don’t rely on that.)
  • Instructor Office Hours in Supernode will be fully offered starting next week. View them at http://berkie.ee/HOPEOH

University of California, Berkeley

IEEE Student Branch

9 of 73

Attendance Logistics

Come to class the first two weeks and fill out the ATTENDANCE QUIZ on our website.

  • To make sure you’re not dropped!
  • Attendance password is written on the board.

Attendance is also part of your semester grade.

  • Fill it out every week!

University of California, Berkeley

IEEE Student Branch

10 of 73

Logistics - Intro to HOPE Quiz

  • An evaluation of your 16B/ME100/circuits knowledge to gauge what we need to teach this semester
    • First half is technical knowledge we will assume you already know
    • 2nd half is for seeing any advanced concepts you may already know
    • This is graded on completion; however, if you find the content of the first half very challenging, please consider taking HOPE a future semester or reach out to staff to get resources to build the technical knowledge you’re missing
    • Due Sept. 12th (Friday before Add/Drop Deadline)

University of California, Berkeley

IEEE Student Branch

11 of 73

Logistics - Assignments

  • Lab Assignments
    • Light Sensor
    • Soldering!
    • USB Charger
    • Interactive Trinket

<- You’ll be starting this one today!

University of California, Berkeley

IEEE Student Branch

12 of 73

Logistics - Project

  • Self-directed final project
  • Groups of 3-4 people
  • Funding provided if desired

University of California, Berkeley

IEEE Student Branch

13 of 73

Logistics - Grading

  • Three main components:
    1. Lab Assignments (45%)
    2. Participation (15%)
      • Attendance (and actively working on labs / course material through 9pm)
      • Can miss 1 for full credit
      • Make a post on Ed for excused absences beyond this
    3. Final Project (40%)

University of California, Berkeley

IEEE Student Branch

14 of 73

Minor Side-Tangent

HOPE is an IEEE Committee!

Want to get more involved or considering helping out with HOPE on the backend?

Interested in working on Technical Projects, Decals, Industry Relations, and more?

University of California, Berkeley

IEEE Student Branch

15 of 73

IEEE: Who We Are

  • Host Company Info Sessions & Career Fairs
  • Professional Development Workshops
  • Mentorship Events and Fun Socials!
  • Build Software & Hardware Projects
  • Connect with National IEEE Student Branches
  • Participate in IEEE Competitions & Hackathons
  • Run Four Technical Decals
  • Join a welcoming and inclusive community!

University of California, Berkeley

IEEE Student Branch

16 of 73

IEEE: What’s In Store for Fall ‘25!

  • Corporate events (info sessions, tech talks, etc.)
    • Apple, TSMC, Digikey, and more!
  • Projects
    • IEEE-Time: Full-stack software tool
    • SIEEECure: FPGA-based security module
  • Activities
    • Ice skating, SF, and more!
    • HOPE & Micromouse DeCals (and new Decals too!)

University of California, Berkeley

IEEE Student Branch

17 of 73

IEEE: Committees

  • Teaching
    • HOPE, Micromouse, EECS 151 Tapeout (NEW!), �APE (NEW!) DeCal committees
  • Member Development
    • ProDev & Activities committees
  • Industrial Relations Committee
  • Technical
    • TechOps Committees

University of California, Berkeley

IEEE Student Branch

18 of 73

IEEE: Upcoming Events

  • Astera Labs Info Session: 9/4, 6-7:30pm @ HMMB 290
  • Apple New Silicon Initiative Kickoff: 9/5, 11-1pm @ Sutardja Dai Hall
  • IEEE Infosession 1: 9/5 7-8PM @ Soda 306 HP Auditorium

University of California, Berkeley

IEEE Student Branch

19 of 73

IEEE: How you can join!

  • General member sign-up:
    • No essays, no interviews, all are welcome!
    • Rolling Admissions
  • Committee Officer Application:
    • Applications due 9/19, 11:59pm
  • Project Member Application:
    • Applications due 9/19, 11:59pm
    • If you’re interested in leading a project, apply to Techops!

University of California, Berkeley

IEEE Student Branch

20 of 73

Questions?

University of California, Berkeley

IEEE Student Branch

21 of 73

Goals for today

  • Students will:
    • Understand what a PCB is
    • Be motivated to learn PCB design
    • Have a basic understanding of the overall PCB design process
    • Be prepared to create a schematic

University of California, Berkeley

IEEE Student Branch

22 of 73

What is a PCB?

Printed Circuit Board

University of California, Berkeley

IEEE Student Branch

23 of 73

What is a PCB?

Printed Circuit Board

University of California, Berkeley

IEEE Student Branch

24 of 73

What is a PCB?

University of California, Berkeley

IEEE Student Branch

25 of 73

What is a PCB?

Macbook Pro Logic Board

University of California, Berkeley

IEEE Student Branch

26 of 73

What is a PCB?

Starlink Satellite Internet Antenna

University of California, Berkeley

IEEE Student Branch

27 of 73

What is a PCB?

University of California, Berkeley

IEEE Student Branch

28 of 73

What is a PCB?

SteamVR Tracking Reference Design - Tundra Labs

Apple Watch

University of California, Berkeley

IEEE Student Branch

29 of 73

Why Make PCBs?

  • Printed circuit boards (PCBs) are the backbone of almost all electronic hardware design
  • Provide form (holds everything together mechanically) and function (makes electrical connections) or more
  • Better, cheaper, and more reliable than alternatives

University of California, Berkeley

IEEE Student Branch

30 of 73

What Alternatives?

Wire wrap

Dead bug

Breadboard

Point-to-point

University of California, Berkeley

IEEE Student Branch

31 of 73

Why learn PCB design?

  • You want to make electrical systems in the 21st century for:
    • Electrical/electronics engineering jobs
    • Research
    • Student project teams
    • Fun!
  • You want to understand the challenges with bringing a circuit to life
    • Circuits exist in real life, and real life is messy!

University of California, Berkeley

IEEE Student Branch

32 of 73

Why learn PCB design?

University of California, Berkeley

IEEE Student Branch

33 of 73

What is HOPE?

  • HOPE is:
    • Engineering Design Class
      • PCB-related design problems require…
        • PCB-related design solutions
    • Hands-on experience with PCB design software
    • Practical experience with soldering, bringup, and test
  • HOPE is not:
    • A course in circuit design
    • An advanced course in a specific EE discipline

University of California, Berkeley

IEEE Student Branch

34 of 73

HOPE:

University of California, Berkeley

IEEE Student Branch

35 of 73

What is a PCB?

Printed Circuit Board

University of California, Berkeley

IEEE Student Branch

36 of 73

What is a PCB?

  • “Sandwich” of conductive copper layers separated with non-conductive substrate
  • Mechanically and electrically supports circuits

University of California, Berkeley

IEEE Student Branch

37 of 73

PCB Features

  • Tracks/Traces — make electrical connections
    • Wires but on the same layer (of cake)
  • Pads — make connections to components
    • Fat copper areas that you can stick things to
    • Aka the frosting you can stick cherries on
  • Vias — holes with electrically conductive plating
    • Wires but between layers (of cake, like jelly filling)

Via

Track/Trace

Pad

Component

University of California, Berkeley

IEEE Student Branch

38 of 73

PCB Features

Through hole technology (THT) Surface-mount devices (SMD)

University of California, Berkeley

IEEE Student Branch

39 of 73

PCB Design Tools

EDA = ECAD

Electronic Design Automation

Electronic Computer Aided Design

University of California, Berkeley

IEEE Student Branch

40 of 73

PCB Design Tools

Back before ECAD software was commonplace…

PCB layouts were drawn by hand...

University of California, Berkeley

IEEE Student Branch

41 of 73

Survey of PCB EDA Tools

More expensive = more features = more Hz and better? library management

(among other things)

University of California, Berkeley

IEEE Student Branch

42 of 73

  • EDA Software we will be using in HOPE
  • Free, open-source (GPLv3)
  • Windows, macOS, Linux, BSD compatible
  • First released in 1992 at IUT de Grenoble, now receives CERN funding, part of Linux Foundation
  • Schematic capture with large default library
    • Direct imports from DigiKey!
    • Widely used, lots of compatibility and 3rd-party libraries

University of California, Berkeley

IEEE Student Branch

43 of 73

General PCB Project Design Flow

University of California, Berkeley

IEEE Student Branch

44 of 73

General PCB Project Design Flow

From: An Intro to KiCad - Part 1: How PCBs are Made | Digikey

This is KiCad’s exact process, actually

From: An Intro to KiCad - Part 1: How PCBs are Made | Digikey

University of California, Berkeley

IEEE Student Branch

45 of 73

General PCB Project Design Flow

From: An Intro to KiCad - Part 1: How PCBs are Made | Digikey

Both in- and out-of-scope for PCB design

PCB design is an iterative process

University of California, Berkeley

IEEE Student Branch

46 of 73

Schematic Flow

  • Draw schematic
    • Communicate function and intent to other designers
  • Perform ERC
    • Computer uses heuristics to determine whether proper circuit connections have been made
    • Only as good as the pin definitions you give it
  • Assign footprints
    • Associate abstract schematics with pads and physical outline of an actual part

University of California, Berkeley

IEEE Student Branch

47 of 73

Layout Flow

  • Layout
    • Place components and route connections on board
  • Perform DRC
    • Verify that layout is manufacturable according to the vendor’s process specifications
  • Output File Generation
    • Generate files that the vendor uses to produce PCBs on real machines. Includes drill files, photomasks, and netlists

University of California, Berkeley

IEEE Student Branch

48 of 73

KiCad Schematics

University of California, Berkeley

IEEE Student Branch

49 of 73

What does a Schematic look like?

University of California, Berkeley

IEEE Student Branch

50 of 73

Schematic to Board

1. Schematic

2. Layout

3. Manufactured Board

*not the full layout

*not the full schematic

University of California, Berkeley

IEEE Student Branch

51 of 73

KiCad Design Flow

Electrical Rule Check (ERC)

Assign Footprints to Schematic

Layout

Design Rule Check (DRC)

Schematic

Output File Generation (Gerbers)

This is pretty much the general design flow for all modern serious PCB ECAD software

PCB design is an iterative process

University of California, Berkeley

IEEE Student Branch

52 of 73

KiCad Design Flow

Electrical Rule Check (ERC)

Assign Footprints to Schematic

Layout

Design Rule Check (DRC)

Schematic

Output File Generation (Gerbers)

This is pretty much the general design flow for all modern serious PCB ECAD software

PCB design is an iterative process

University of California, Berkeley

IEEE Student Branch

53 of 73

Schematics

  1. Defines components in system
    1. Abstract & simple symbols reflect actual parts
  2. Defines connectivity of components in system
  3. Schematics should easily communicate relevant information defined in (1) and (2) to others.

University of California, Berkeley

IEEE Student Branch

54 of 73

Key Schematic Design Rule

Good schematics show you the circuit.

Bad schematics make you decipher them.

  • someone on StackExchange on good circuit design

University of California, Berkeley

IEEE Student Branch

55 of 73

Good Schematics?

What does this do? Which do you prefer?

University of California, Berkeley

IEEE Student Branch

56 of 73

Schematics

  • Defines components in system
    • Abstract & simple symbols reflect actual parts
  • Defines connectivity of components in system
  • Easily communicates above 2 points to both the stakeholders and the computer ECAD program
    • Each involved stakeholder should easily be able to get their relevant information from the schematic

University of California, Berkeley

IEEE Student Branch

57 of 73

Schematics

  • Defines components in system
    • Abstract & simple symbols reflect actual parts
  • Defines connectivity of components in system
  • Schematics should easily communicate relevant information defined in (1) and (2) to others.

University of California, Berkeley

IEEE Student Branch

58 of 73

Components

University of California, Berkeley

IEEE Student Branch

59 of 73

Components

  • Electronic devices of any kind are constructed mainly from a limited set of very basic components

Can you name and draw more non-IC components?

Makes keeping a consistent symbol “alphabet” easy

    • Resistors
    • Capacitors
    • Inductors (L)
    • Switches
    • Diodes
    • Transistors (Q)

University of California, Berkeley

IEEE Student Branch

60 of 73

Components

  • Non-standard components may be represented as boxes with in/out pins
    • ICs are the usual culprit
    • Pins should be organized by function, not only physical position
  • Common functional components (i.e. op-amps, logic gates) can get their own symbol
    • Make sure they use an appropriate�reference designator according to IEEE 315

University of California, Berkeley

IEEE Student Branch

61 of 73

Components: in ECAD

  • Components/Parts are symbols made up of:
    • Pins: special “line-like” objects that the program acknowledges as corresponding to an electrical connection point on the part
    • Graphics: make the symbol look like the symbol. Solely for human communicative purposes
    • Designator: unique name/identifier for the component
    • Metadata: depending on the program, can range from nonexistent (Fritzing) to insane (Altium Designer)

University of California, Berkeley

IEEE Student Branch

62 of 73

Schematics

  • Defines components in system
    • Abstract & simple symbols reflect actual parts
  • Defines connectivity of components in system
  • Schematics should easily communicate relevant information defined in (1) and (2) to others.

University of California, Berkeley

IEEE Student Branch

63 of 73

Connectivity (Nets)

University of California, Berkeley

IEEE Student Branch

64 of 73

Connectivity - Nets on a PCB

Nets describe electrical connectivity

Schematic

Layout

Nets are connected on a PCB with (conductive) copper traces and vias

University of California, Berkeley

IEEE Student Branch

65 of 73

Connectivity - Pins on a PCB

Schematic

Layout

Pins belonging to net are connected in schematic and layout

Pins become pads where parts are assembled to the board

University of California, Berkeley

IEEE Student Branch

66 of 73

Circuit Connectivity: Netlists

  • A netlist is defined by your schematic
    • Net: list of component pins that are all connected to each other
    • Netlist: dictionary of nets, each net is uniquely named

List of pins connected to net 5

University of California, Berkeley

IEEE Student Branch

67 of 73

Schematics in ECAD

University of California, Berkeley

IEEE Student Branch

68 of 73

PCB ECAD Specific Schematic Info

  • Couple of additional features in digital schematics
    • Everything exists on a grid
      • Components, pins, wires, easily snap together
    • All components are named
      • These follow the component designators mentioned earlier, + a number
        • Why might this be necessary for PCBs?
    • All nets are named
      • Automatically, though net labels can be used to force a name to a net

University of California, Berkeley

IEEE Student Branch

69 of 73

KiCad Command Summary

Select

Highlight net

(A)dd Component

(P)ower

(W)ire

Bus

Wire to Bus

No Connect (Q)

Wire Junction

Net (L)abel

Global Label

Graphic Polygon

Graphic Lines

Add Image

Eraser

University of California, Berkeley

IEEE Student Branch

70 of 73

Questions?

University of California, Berkeley

IEEE Student Branch

71 of 73

Enrollment (Again)

  • If you’re still not sure whether this is the class for you, talk to us!
  • If you haven’t already, fill out the attendance form
    • Linked at top of https://hope.berkie.ee/
    • Waitlisted students too
  • EE 198-002 (Wed) and EE 198-004 (Thurs)
  • 2 (real!) Unit P/NP
  • Join Discord (if you want)! https://discord.gg/S8rmBNKQ

University of California, Berkeley

IEEE Student Branch

72 of 73

Feedback Form

  • We have students from a variety of backgrounds, so we want to make HOPE as accessible as possible.
  • Feedback form: https://berkie.ee/hope-fa25-anonymous-comments
    • Help us make this your ideal class!
  • Embody the (friendly) hobbyist spirit!
    • Help each other out & learn from each other!

University of California, Berkeley

IEEE Student Branch

73 of 73

The fun stuff - Lab 1: Light Sensor

University of California, Berkeley

IEEE Student Branch