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1. SiO₂ properties and applications.
2. Thermal oxidation basics.
3. Manufacturing methods and equipment.
4. Measurement methods.
5. Deal-grove model (linear parabolic model).
6. Thin oxide growth, dependence on gas pressure and crystal orientation
7. Cl-containing gas, 2D growth, substrate doping effect .
8. Interface charges, dopant redistribution.

Si(s) + O₂(g) → SiO₂(s)

Chapter 6 Thermal oxidation and the Si/SiO₂ interface

NE 343: Microfabrication and thin film technology

Instructor: Bo Cui, ECE, University of Waterloo; http://ece.uwaterloo.ca/~bcui/

Textbook: Silicon VLSI Technology by Plummer, Deal and Griffin

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Properties of thermally grown SiO₂

• It is amorphous.
• Stable, reproducible and conformal SiO₂ growth
• Melting point: 1700°C
• Density: 2.21 g/cm³ (almost the same as Si that is 2.33 g/cm³)
• Crystalline SiO₂ [Quartz] = 2.65gm/cm³

• Atomic density: 2.3×10²² molecules/cm³

(For Si, it is 5×10²² atoms/cm³)

• Refractive index: n=1.46
• Dielectric constant: ε=3.9 (why not =n²?)
• Excellent electrical insulator: resistivity ρ > 10²⁰ Ωcm, energy gap E_g=8-9 eV.
• High breakdown electric field: >10⁷ V/cm

Conformal growth

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The perfect interface between Si and SiO₂ is one major reason why Si is used for semiconductor devices (instead of Ge…)

Thermal oxide (amorphous)

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Si substrate

(single crystal)

The Si/SiO₂ interface

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Application of SiO₂ in IC industry

Very good etching selectivity between Si and SiO₂ using HF

STI: shallow trench isolation

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Diffusion mask for common dopants

SiO₂ can provide a selective mask against

diffusion at high temperatures. (D_SiO2 << D_si)

Oxides used for masking are ~0.5-1μm thick.

SiO₂ masks for B and P

Can also be used for mask against ion implantation

Diffusion time (hr)

Mask thickness (μm)

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Gate oxide, only 0.8nm thick!

As insulation material between interconnection levels and adjacent devices

Use of oxide in MOSFET

LOCOS: local oxidation isolation; STI: shallow trench isolation

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Local Oxidation of Si (LOCOS)

Fully recessed process attempts to minimize bird’s peak.

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For nanofabrication: oxidation sharpening for sharp AFM tips or field emitters for display

Ding, “Silicon Field Emission Arrays With Atomically Sharp Tips: Turn-On Voltage and the Effect of Tip Radius Distribution”, 2002.

Field emission display (FED)

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Oxide Structure

Basic structure of silica: a silicon atom tetrahedrally bonds to four oxygen atoms

The structure of silicon-silicon dioxide interface: some silicon atoms have dangling bonds.

Amorphous tetrahedral network

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Single crystal (quartz)

2.65 g/cm³

Amouphous (thermal oxide). 2.21 g/cm³

Oxide Structure

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1. SiO₂ properties and applications.
2. Thermal oxidation basics.
3. Manufacturing methods and equipment.
4. Measurement methods.
5. Deal-grove model (linear parabolic model).
6. Thin oxide growth, dependence on gas pressure and crystal orientation
7. Cl-containing gas, 2D growth, substrate doping effect .
8. Interface charges, dopant redistribution.

Chapter 6 Thermal oxidation and the Si/SiO₂ interface

NE 343 Microfabrication and thin film technology

Instructor: Bo Cui, ECE, University of Waterloo

Textbook: Silicon VLSI Technology by Plummer, Deal and Griffin

Dry and wet oxidation

Dry oxidation: Si(s) + O₂(g) → SiO₂(s); Wet/steam oxidation: Si(s) + 2H₂O(g) → SiO₂(s) + 2H₂(g)

• Both typically 900-1200°C, wet oxidation is about 10× faster than dry oxidation.
• Dry oxide: thin 0.05-0.5μm, excellent insulator, for gate oxides; for very thin gate oxides, may add nitrogen to form oxynitrides.
• Wet oxide: thick <2.5 μm, good insulator, for field oxides or masking. Quality suffers due to the diffusion of the hydrogen gas out of the film, which creates paths that electrons can follow.
• Room temperature Si in air creates “native oxide”: very thin ~1-2nm, poor insulator, but can impede surface processing of Si.
• Volume expansion by 2.2× (=1/0.46), so SiO₂ film has compressive stress.

Si wafer

X_ox is final oxide thickness

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1. SiO₂ properties and applications.
2. Thermal oxidation basics.
3. Manufacturing methods and equipment.
4. Measurement methods.
5. Deal-grove model (linear parabolic model).
6. Thin oxide growth, dependence on gas pressure and crystal orientation
7. Cl-containing gas, 2D growth, substrate doping effect .
8. Interface charges, dopant redistribution.

Chapter 6 Thermal oxidation and the Si/SiO₂ interface

NE 343 Microfabrication and thin film technology

Instructor: Bo Cui, ECE, University of Waterloo

Textbook: Silicon VLSI Technology by Plummer, Deal and Griffin

14

Thermal silicon oxidation methods

A three-tube horizontal furnace with multi-zone temperature control

Vertical furnace

(not popular)

Wet oxidation using H₂ and O₂ is more popular (cleaner) than using H₂O vapor.

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• The tubular reactor made of quartz or glass, heated by resistance.
• Oxygen or water vapor flows through the reactor and past the silicon wafers, with a typical velocity of order 1cm/s.

Thermal oxidation equipment

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1. Clean the wafers (RCA clean, very important)
2. Put wafers in the boat
3. Load the wafers in the furnace
4. Ramp up the furnace to process temperature in N₂ (prevents oxidation from occurring)
5. Stabilize
6. Process (wet or dry oxidation)
7. Anneal in N₂. Again, nitrogen stops oxidation process.
8. Ramp down

Thermal oxidation in practice

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1. SiO₂ properties and applications.
2. Thermal oxidation basics.
3. Manufacturing methods and equipment.
4. Measurement methods (mechanical, optical, electrical).
5. Deal-grove model (linear parabolic model).
6. Thin oxide growth, dependence on gas pressure and crystal orientation
7. Cl-containing gas, 2D growth, substrate doping effect .
8. Interface charges, dopant redistribution.

Chapter 6 Thermal oxidation and the Si/SiO₂ interface

NE 343 Microfabrication and thin film technology

Instructor: Bo Cui, ECE, University of Waterloo

Textbook: Silicon VLSI Technology by Plummer, Deal and Griffin

18

Oxide etched away by HF over part of the wafer and a mechanical stylus is dragged over the resulting step.

Surface profilometry (Dektak): mechanical thickness measurement

AFM can also be used for thickness measurement.

(AFM: atomic force microscopy)

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Thickness determination by looking the color

• Oxide thickness for constructive interference (viewed from above φ=0^o) X_o=kλ/2n, n=1.46, k=1, 2, 3…
• Our eye can tell the color difference between two films having 10nm thickness difference.

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• After quarter wave plate, the linear polarized light becomes circular polarized, which is incident on the oxide covered wafer.
• The polarization of the reflected light, which depends on the thickness and refractive index (usually known) of the oxide layer, is determined and used to calculate the oxide thickness.
• Multiple wavelengths/incident angles can be used to measure thickness/refractive index of each film in a multi-film stack.

Optical thickness measurement: ellipsometry

Very accurate (1nm accuracy)

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Electrical thickness measurement: C-V of MOSFET

Substrate is N-type. Electron is majority carrier, hole is minority carrier.

1. Accumulation: positive gate voltage attracts electrons to the interface.
2. Depletion: negative gate bias pushes electrons away from interface. No charge at interface. Two capacitance in series.
3. Inversion: further increase (negative) gate voltage causes holes to appear at the interface.

Small AC voltage is applied on top of the DC voltage for capacitance measurement.

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Effect of frequency for AC capacitance measurement

At/after inversion:

For low frequency, (minority) charge generation at the interface can follow the AC field to balance the charge at the gate, so C_inv=C_ox.

For high frequency, the gate charge has to be balanced by the carrier deep below the interface, so C_inv^-1 = C_ox^-1 + C_Si^-1.

Deep depletion: for high scanning speed (the DC voltage scan fast into large positive voltage), depletion depth X_d must increase to balance the gate charge.

Parameter from C-V measurement:

• Dielectric constant of Si & SiO₂
• Capacitor area
• Oxide thickness
• Impurity profile in Si
• Threshold voltage of MOS capacitor