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Charge Readout Architectures for Kilotonne-scale LArTPCs

Brooke Russell

UCR CECI Workshop on Detector Science (CWODS)

July 2, 2026

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Supernova Neutrino Burst (SNB) Detection

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EPJC 81 (2021) 5, 423

PRD 111 (2025) 9, 092006

10-2

10-1

1

Time (seconds)

 

Neutrino mass ordering via SNB detection

 

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DUNE Far Detectors

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DUNE Phase I with projective readout LArTPCs (2029, 2030)

4th detector in DUNE Phase II technology TBD (2036)

3rd detector in DUNE Phase II with LArTPC technology (2034)

FERMILAB-PUB-25-0244-LBNF

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Physics Motivation for a Pixelated Readout Far Detector:�Enhanced long-baseline neutrino oscillation physics program

  • 2D versus 3D differential comparison shows non-negligible reconstruction performance improvement with 3D readout
    • Event classification
    • Neutrino ID classification
    • Final state topology ID

  • Improved ability to extrapolate detector responses from ND to FD
    • A pixelated readout will likely offer greater cancellation of detector response systematics using ND-LAr data than other alternative readout schemes

  • Enhanced detection capability of unexpected O(1) MeV phenomena
    • All pixels are continuously active, self-triggering at O(100) keV thresholds

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2D versus 3D reconstruction quantitative performance characterization              JINST 15 P04009

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Physics Motivation for a Pixelated Readout Far Detector:�Enhanced low-energy O(MeV) physics program

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Highly efficient detection, characterization of core-collapse supernova neutrinos

Studied with QPix readout Phys. Rev. D106 (2022) 3, 032011

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Physics Motivation for a Pixelated Readout Far Detector:�Enhanced low-energy O(MeV) physics program

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Highly efficient detection, characterization of core-collapse supernova neutrinos

~200 keV pixel thresholds with first generation LArPix-v2a, -v2b system

Studied with QPix readout Phys. Rev. D106 (2022) 3, 032011

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Ionization Sensing Technology-Dependent Tradeoffs

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Projective readout (strips or wires): native 2D --> reconstructed 3D  

Pixelated readout:

inherently 3D

Far detector 1 & 2 technology

Near detector technology & proposed far detector 3

  • Forced trigger with continuous sampling
  • Sense plane position is topology dependent, indeterminate with single plane
  • Multiple redundant charge measurements

  • Zero-suppressed, self-trigger
  • Sense plane position is absolute
  • Sub-threshold charge is irrecoverable
  • Single measurement

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Signal Detection in LArTPCs

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LArTPC charge sensors measure the coherent sum of induced currents from the totality of the ionization charge profile

Beware: subtle topology dependencies and artifacts!

Necessitates deconvolution in time and wire domains

JINST 13 (2018) 07, P07006

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Off-beam Triggering Capabilities

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EPJC 81 (2021) 5, 423

JINST 19 (2024) 08, T08004

2604.23966 [physics.ins-det]

 

Technical limitation from induction response & data size can be overcome with development of on-FPGA real-time signal processing

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LArPix Charge Readout System-level Design

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Charge readout for the DUNE

liquid argon near detector (ND-LAr)

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LArPix Analog Front-End

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5.4mm

64-channel SoC, in 130nm

Front-end Amplifier

SAR Digitizer

Self-triggering Discriminator

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LArPix Digital Back-End

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5.4mm

64-channel SoC, in 130nm

Digital control: data aggregation, amplifier configuration, inter-chip communication

Data transmitted on every rising clock edge (10 Mbit at 10 MHz CLK)

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Digital I/O

Custom tunable low-voltage digital transmitter and receiver

  • Similar to LVDS in concept, but much lower power: O(10 µW) per transmitter & receiver
  • Highly-tunable loop current and termination resistance supports multiple modes of operation (chip-to-chip, chip-to-controller)
  • Optional mode for automatic transmitter power-down when no data

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off-tile I/O

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Hydra I/O

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Example failed chip

Example 5x5 pixel tile network

  • Each ASIC capable of configurable I/O in any cardinal direction
  • I/O can occur between any neighboring chips on pixel tile
  • ASIC network constructed by explicit configurable connection between neighboring ASICs in a determined fashion

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DUNE’s First Neutrinos with the 2x2 Demonstrator

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Collected 1.5E19 protons on target corresponding to ~30k (anti)neutrino interactions in LArTPC volume

  • Eight optically isolated TPCs in 2.4 tonne active mass

  • 337k charge-sensitive pixels at ~4 mm pitch operated at 5 kiloelectron pixel threshold

  • 29% photocoverage read out by 384 SiPMs

Additional beam anticipated Fall 2026

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Pixelated System Architecture Scaling

  • FD-specific technical requirements (already funded with work in progress)
    • Mechanical engineering for frame and VD interfaces
    • ASIC engineering to multiplex multiple anode tiles
    • Pixel data driven over 30 m of cable to warm-side electronics
    • Electronics response optimization

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Top Anode Plane: Pixel CRP

Bottom Anode Plane: Pixel CRP

Installation sequence, constraints, schedule, cost are commensurate with strip CRP

Top & Bottom Pixel CRP readout:

  • 160 CRPs instrumenting 1440 m2
  • 114M pixels driven by 1.79M ASICs on 11.2k tiles

NDLAr Pixel readout:

  • 200 m2 instrumented anode area
  • 14M pixels driven by 224k ASICs on 1400 tiles

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Pixelated System Architecture Scaling

  • FD-specific technical requirements (already funded with work in progress)
    • Mechanical engineering for frame and VD interfaces
    • ASIC engineering to multiplex multiple anode tiles
    • Pixel data driven over 30 m of cable to warm-side electronics
    • Electronics response optimization

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Existing 3m-by-3m CRP anode to be replaced with LArPix anode

O(10) cm TPC drift distance

FD vertical drift anode support structure

CERN ColdBox

anticipate September 2026 operations

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Pixelated System Architecture Scaling

  • FD-specific technical requirements (already funded with work in progress)
    • Mechanical engineering for frame and VD interfaces
    • ASIC engineering to multiplex multiple anode tiles
    • Pixel data driven over 30 m of cable to warm-side electronics
    • Electronics response optimization

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Multiplexer ASIC for Data and Clock Aggregation and Propagation

  • A data aggregator to reduce the cable plant by a factor of 8
  • 160 Mbps data output in a 12 byte superpacket
  • Roughly 4 µW/LArPix channel power overhead
  • Same package and CMOS process as existing LArPix-v3 ASIC

Taped out last month!

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Pixelated System Architecture Scaling

  • FD-specific technical requirements (already funded with work in progress)
    • Mechanical engineering for frame and VD interfaces
    • ASIC engineering to multiplex multiple anode tiles
    • Pixel data driven over 30 m of cable to warm-side electronics
    • Electronics response optimization

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Replace one bottom strip CRP with a pixel CRP

Install a pixel CRP in the bottom anode plane alongside a strip CRP for side-by-side performance comparison in the ProtoDUNE-III operation

Operations as early as end of CY2028

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LArPix ASIC Reset Schemes

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  • Front-end periodic reset at a configurable cadence on a channel rolling or chip-synchronous basis
    • Highly effective in mitigating detector environment noise
      • Microphonics
      • Cryocooler power cycling
    • Long-range induction mitigation
  • 100 ns AFE deadtime incurred with each reset

Reset at 2.4 Hz

Reset at 2.4 kHz

Pixel pedestal RMS (50k channels)

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LArPix ASIC Triggering Schemes

  • Self-trigger reset (nominal operating mode): digitize and drain charge after threshold crossed
  • Cross-trigger reset: digitize and drain sub-threshold charge based on self-trigger of another pixel
  • External-trigger reset: digitize and drain sub-threshold charge based on external signal
  • Periodic-trigger reset: periodically digitize and drain sub-threshold charge at fixed cadence on a channel rolling or chip-synchronous basis
  • Optional burst modes
    • Fixed burst: process N hit cycles for each self-trigger
    • ADC threshold: continue to process hit cycle until an ADC dataword ceiling (or floor) is exceeded
    • ADC settle: continue to process hit cycles until change in ADC value is below set value

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ADC settle triggering scheme

MIP track ~parallel to anode

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SoLAr

  • Combined light+charge calorimetry from the same plane of view (anode) for increased detection of low energy (5-20 MeV) neutrino events
  • Distributed array of VUV SiPMs incorporated into pixelated charge readout plane
    • LArPix pixel readout + LightPix SiPM readout

v1 prototype

v2 prototype

Proposed ProtoDUNE III charge+light integrated anode tile

EPJC 81 (2021) 5, 423

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LightPix ASIC

  • Cryo-compatible 'pixelated' SiPM readout with unique channel for each SiPM
    • 32 "super channels" with sub-ns timing + calorimetry per ASIC
    • Synergistic system architecture with LArPix pixelated charge readout
  • Fully differential clock and digital I/O

TDC resolution and linearity < 1 ns

Demonstrated multi-PE discrimination and single-PE self-trigger efficiency

Triggers (area normalized)

ADC word

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Summary

  • Pixelated readout at the DUNE far detector has the potential to enhance overall DUNE physics
    • Long-baseline neutrino oscillation physics sensitivities
    • Improved signal detection, characterization at the O(1) MeV scale

🡺 Enhanced sensitivity to the unexpected

  • We have a credible path to build a charge readout system instrument >10 kiloton LAr
    • Far detector mechanical interfaces 🡺 pixel CRP CERN Cold Box operations in Sept. 2026
    • MADCAP ASIC testing this fall
    • Data driven at scale 🡺 Prospective ProtoDUNE-III operations in 2028
    • On-going incremental improvements to LArPix ASIC design and performance

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LArPix-v3 ASIC

  • Design ported from 180 nm to 130 nm CMOS
  • Improved analog front-end buffer
    • Higher signal-to-noise ratio relative to previous design
  • Moved to 10-bit SAR ADC
    • Differential design with bi-directional switching, reducing area and power
    • With asynchronous logic, internally generated clock speeds ADC conversion by ~10x
  • Data transmission on both (10 MHz) clock edges
  • Optional digital correlated double-sampling
  • Improved data integrity features and diagnostics
    • Independent configuration FIFO
    • Magic number for configuration packets
    • Fully differential analog monitor

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Cosmic rays imaged with LArPix-v3