ADC, DAC,

AND SENSOR

INTERFACING

Chapter 13

Table 13-1: Resolution vs. Step Size for ADC

n-bit Number of steps Step Size (mV)

8 256 5/256 = 19.53

10 1024 5/1024 = 4.88

12 4096 5/4096 = 1.2

16 65536 5/65536 = 0.076

Notes: V_CC = 5 V

Step size (resolution) is the smallest change that can be discerned by an ADC.

Figure 13-1. ADC0804 Chip (testing ADC0804 in free running mode)

Table 13-2: V_ref/2 Relation to V_in Range (ADC0804)

Figure 13-2. Read and Write Timing for ADC0804

Figure 13-3. 8051 Connection to ADC0804 with Self-Clocking

Figure 13-4. 8051 Connection to ADC0804 with Clock from XTAL2 of the 8051

Figure 13-5. ADC0808/0809

Table 13-3: ADC0808/0809 Analog Channel Selection

Selected Analog Channel C B A

IN0 0 0 0

IN1 0 0 1

IN2 0 1 0

IN3 0 1 1

IN4 1 0 0

IN5 1 0 1

IN6 1 1 0

Table 13-4: V_ref Relation to V_in Range for ADC0808/0809

Figure 13-6. Selecting a Channel and Read Timing for ADC0809

Figure 13-7. 8051 Connection to ADC0809 for Channel 1

Figure 13-8. ADC0848 Chip

Table 13-5: ADC0848 V_ref vs. Step Size

Figure 13-9. ADC0848 Block Diagram

Table 13-6: ADC0848 Analog Channel Selection (Single-Ended Mode)

Figure 13-10. Selecting a Channel and Read Timing for the ADC0848

Figure 13-11. 8051 Connection to ADC0848 for Channel 2

Figure 13-12. MAX1112 Chip

Figure 13-13. MAX1112 Serial ADC Block Diagram

Figure 13-14. MAX1112 Control Byte

Start The MSB (D7) must be high to define the beginning of the control byte.

It must be sent in first.

SEL2 SEL1 SEL0 CHANNEL SELECTION (SINGLE-ENDED MODE)

0 0 0 CHAN0

0 0 1 CHAN1

0 1 0 CHAN2

0 1 1 CHAN3

1 0 0 CHAN4

1 0 1 CHAN5

1 1 0 CHAN6

1 1 1 CHAN7

​

UNI/BIP 1 = unipolar: Digital data output is binary 00 - FFH.

0 = bipolar: Digital data output is in 2’s complement.

SGL/DIF 1 = single-ended: 8 channels of single-ended with COM as reference

0 = differential: Two channels (eg., CH0 - CH1) are differential.

PD1 1 = fully operational

0 = power-down: Power down to save power using software.

PD0 1 = external clock mode: The conversion speed is dictated by SCLK.

0 = internal clock mode: The conversion speed is dictated internally,

and the SSTRB pin goes high to indicate end-of-conversion (EOC).