RISC V Datapath II

We recommend you download the PPTX and play the animation on each slide!

CS61C

Great Ideas

in�Computer Architecture

(a.k.a. Machine Structures)

UC Berkeley�Teaching Professor�Dan Garcia

cs61c.org

Garcia, FA25

20-Datapath II (1)

Our Datapath So Far: Arithmetic/Logic

Imm. Gen

inst[31:20]

addr

inst

​

IMEM

add

R[rs1]

clk

clk

imm[31:0]

pc

+4

alu

inst[31:0]

ImmSel

?

RegWEn

?�

BSel

?

ALUSel

?

Control Logic

pc+4

0

1

Imm. Gen

A

ALU

B

Bold white wires carry data.

Thin orange wires are control logic.

R[rs2]

inst[11:7]

inst[19:15]

inst[24:20]

Review

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

Garcia, FA25

20-Datapath II (2)

I-Type: Immediate Block

[for next time]

Agenda

• Adding I-Type
• Implementing Loads
• Implementing Stores
• Adding B-Type (Branches)
• Designing the Immediate Generation Block
• Adding Jumps jal, jalr
• Adding U-Type

Garcia, FA25

20-Datapath II (3)

Implementing the addi Instruction

• Suppose we add a new instruction: addi, RV32I I-Type:

​

​

​

​

• The addi instruction updates the same two states as before.�But we now need to build an immediate imm!
• RegFile Reg[rd] = Reg[rs1] + imm
• PC PC = PC + 4

addi rd rs1 imm

OP-IMM

“add”

Garcia, FA25

20-Datapath II (4)

1. New MUX to Select Immediate for ALU

addr

inst

​

IMEM

add

R[rs1]

clk

clk

R[rs2]

pc

+4

alu

inst[31:0]

RegWEn

1�

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

A

ALU

B

inst[11:7]

inst[19:15]

inst[24:20]

BSel

1

ALUSel

Add

0

1

1. Control line BSel=1 selects the generated immediate imm for ALU input B.

Garcia, FA25

20-Datapath II (5)

2. New Block to Generate 32-bit Immediate

addr

inst

​

IMEM

add

R[rs1]

clk

clk

R[rs2]

pc

+4

alu

inst[31:0]

RegWEn

1�

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

A

ALU

B

inst[11:7]

inst[19:15]

inst[24:20]

0

1

BSel

1

Split and get the upper 12 bits of inst.

ALUSel

Add

1. Control line BSel=1 selects the generated immediate imm for ALU input B.

2. Immediate Generation Block builds a 32-bit immediate imm from instruction bits.

Garcia, FA25

20-Datapath II (6)

Tracing/Lighting the addi Datapath

Imm. Gen

inst[31:20]

addr

inst

​

IMEM

add

inst[11:7]

inst[19:15]

inst[24:20]

R[rs1]

clk

clk

R[rs2]

imm[31:0]

pc

+4

inst[31:0]

ImmSel

RegWEn�

BSel

ALUSel

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

0

1

Imm. Gen

A

ALU

B

alu

R[rs2]

pc

Data inst[24:20] still feeds into Reg[], which still outputs R[rs2].

However, control Bsel=1 means R[rs2] data line is ignored.

Increment PC to next instruction.

Write ALU output to destination register.

Control line BSel=1 selects the generated immediate imm for ALU input B.

Immediate Generation Block builds a 32-bit immediate imm from instruction bits.

ImmSel

I

RegWEn

1�

BSel

1

ALUSel

Add

Garcia, FA25

20-Datapath II (7)

Implementing Loads

Agenda

• Adding I-Type
• Implementing Loads
• Implementing Stores
• Adding B-Type (Branches)
• Designing the Immediate Generation Block
• Adding Jumps jal, jalr
• Adding U-Type

Garcia, FA25

20-Datapath II (8)

Implementing the lw Instruction

• lw uses I-Type:

​

​

​

• Similar datapath to addi, but creates�an address (not the final value stored).
• State element access now includes a memory read!
• DMEM (read word at address addr)
• RegFile Reg[rs1] # read; Reg[rd] # write
• PC PC = PC + 4

lw rd imm(rs1)

LOAD

“load word”

addr = (Base register rs1)

+ (sign-extended imm offset)

Garcia, FA25

20-Datapath II (9)

Saving Memory Read to RegFile

clk

mem

1

0

alu

Imm. Gen

inst[31:20]

addr

inst

​

IMEM

add

R[rs1]

clk

clk

imm[31:0]

pc

+4

inst[31:0]

ImmSel

RegWEn�

BSel

ALUSel

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

0

1

Imm. Gen

A

ALU

B

R[rs2]

inst[11:7]

inst[19:15]

inst[24:20]

Read memory at address�alu = R[rs1] + imm.

MemRW

Read

WBSel

0

Garcia, FA25

20-Datapath II (10)

Lighting the LOAD Datapath

Imm. Gen

inst[31:20]

addr

inst

​

IMEM

add

inst[11:7]

inst[19:15]

inst[24:20]

R[rs1]

clk

clk

R[rs2]

imm[31:0]

pc

+4

inst[31:0]

ImmSel

RegWEn�

BSel

ALUSel

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

0

1

Imm. Gen

A

ALU

B

R[rs2]

pc

Increment PC to next instruction.

Write loaded memory value mem to register.

ALU computes�address alu =� R[rs1] + imm.

Immediate Generation Block builds a 32-bit immediate imm.

rdata

addr

DMEM

wdata

clk

mem

1

0

alu

Load uses all five stages of the datapath!

Read memory at address alu.

Garcia, FA25

20-Datapath II (11)

RV32I Can Load Different Widths

• To support narrower loads (lb, lh, lbu, lhu):
• Load 32-bit word from memory;
• Add additional logic to extract correct byte or halfword; and
• Sign- or zero-extend result to 32 bits to write into RegFile.
• Can be implemented with MUX + and a few gates.

[reference; see Proj3]

Garcia, FA25

20-Datapath II (12)

Implementing Stores

Agenda

• Adding I-Type
• Implementing Loads
• Implementing Stores
• Adding B-Type (Branches)
• Designing the Immediate Generation Block
• Adding Jumps jal, jalr
• Adding U-Type

Garcia, FA25

20-Datapath II (13)

Implementing the sw Instruction

• S-Type:

​

​

​

• New Immediate Format:
• addr = (Base register rs1) + (sign-extended imm offset)
• State Elements Accessed:
• DMEM (write R[rs2] to word at address addr)
• RegFile R[rs1] (base address), R[rs2] (value to store)
• PC PC = PC + 4

sw rs2 imm(rs1)

STORE

“store word”

No RegFile write!

Garcia, FA25

20-Datapath II (14)

Updated Blocks for sw

Imm. Gen

inst[31:7]

addr

inst

​

IMEM

add

R[rs1]

rdata

addr

DMEM

wdata

clk

clk

clk

imm[31:0]

pc

+4

mem

inst[31:0]

ImmSel

S

RegWEn

�

BSel

ALUSel

MemRW

Write

WBSel

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

A

ALU

B

Control MemRW=Write saves rs2 to memory on the next rising clock edge.

0

1

Imm. Gen

1

0

Control ImmSel selects how to generate immediate type: I, S.

R[rs2]

inst[11:7]

inst[19:15]

inst[24:20]

R[rs2]

(to discuss later)

Garcia, FA25

20-Datapath II (15)

How to Set sw Control Lines?

Imm. Gen

inst[31:7]

addr

inst

​

IMEM

add

R[rs1]

clk

clk

clk

imm[31:0]

pc

+4

mem

inst[31:0]

ImmSel

S

RegWEn

?

�

BSel

?

ALUSel

Add

MemRW

Write

WBSel

?

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

A

ALU

B

0

1

Imm. Gen

1

0

R[rs2]

inst[11:7]

inst[19:15]

inst[24:20]

RegWEn Bsel WBSel

• Read(0) 0 0
• 0 0 1
• 0 1 0
• 0 1 1
• Write(1) 0 0
• 1 0 1
• 1 1 0
• 1 1 1

Garcia, FA25

20-Datapath II (16)

Garcia, FA25

20-Datapath II (17)

How to Set sw Control Lines RegWEn, BSel, ALUSel?

Imm. Gen

inst[31:7]

addr

inst

​

IMEM

add

R[rs1]

clk

clk

clk

imm[31:0]

pc

+4

mem

inst[31:0]

ImmSel

S

RegWEn

?

�

BSel

?

ALUSel

Add

MemRW

Write

WBSel

?

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

A

ALU

B

0

1

Imm. Gen

1

0

R[rs2]

inst[11:7]

inst[19:15]

inst[24:20]

Select all that apply

Garcia, FA25

20-Datapath II (18)

Lighting the STORE Datapath

Imm. Gen

inst[31:20]

addr

inst

​

IMEM

add

inst[11:7]

inst[19:15]

inst[24:20]

R[rs1]

clk

clk

R[rs2]

imm[31:0]

pc

+4

inst[31:0]

ImmSel

RegWEn�

BSel

ALUSel

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

0

1

Imm. Gen

A

ALU

B

R[rs2]

pc

Increment PC to next instruction.

ALU computes�address alu =� R[rs1] + imm.

Build imm from�S-type instruction.

rdata

addr

DMEM

wdata

clk

mem

1

0

alu

Write memory at address alu.

RegWEn=0 means no write back to RegFile, so “don’t care” (*) about WBSel’s value.

RegWEn Bsel WBSel

• 0 1 0
• 0 1 1

(most unselected data lines omitted from lighting)

Garcia, FA25

20-Datapath II (19)

Adding B-Type (Branches)

Agenda

• Adding I-Type
• Implementing Loads
• Implementing Stores
• Adding B-Type (Branches)
• Designing the Immediate Generation Block
• Adding Jumps jal, jalr
• Adding U-Type

Garcia, FA25

20-Datapath II (20)

B-Type: Conditional Branch

• B-Type (textbook: SB-Type) close to S-Type:

opname rs1 rs2 Label

BRANCH

• New Immediate Format!
• PC state element now conditionally changes:
• RegFile R[rs1], R[rs2] (read only, for branch comparison)
• PC PC = PC + imm (if branch taken)� PC = PC + 4 (otherwise, not taken)

​

Garcia, FA25

20-Datapath II (21)

What do Branches Need to Compute?

Imm. Gen

inst[31:7]

addr

inst

​

IMEM

add

R[rs1]

clk

clk

clk

imm[31:0]

pc

+4

mem

inst[31:0]

ImmSel

RegWEn

�

BSel

ALUSel

MemRW

WBSel

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

A

ALU

B

0

1

Imm. Gen

1

0

R[rs2]

inst[11:7]

inst[19:15]

inst[24:20]

PC = PC + imm

PC = PC + 4

❓

❓

Only one ALU accessible in the same clock cycle. Need more hardware!!

Compare R[rs1] , R[rs2]

✅

add

Garcia, FA25

20-Datapath II (22)

The Branch Comparator Block

Imm. Gen

inst[31:7]

addr

inst

​

IMEM

add

clk

clk

clk

imm[31:0]

pc

+4

mem

inst[31:0]

ImmSel

RegWEn

�

BSel

ALUSel

MemRW

WBSel

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

Imm. Gen

1

0

inst[11:7]

inst[19:15]

inst[24:20]

BrUn: Control�BrLT, BrEq: Output back to Control

Branch Comp.

R[rs1]

alu

A

ALU

B

0

1

BrUn

BrEq

BrLT

​

R[rs2]

Compare R[rs1],R[rs2],�feed result to Control Logic.

PCSel

taken/not taken

0

1

Update PC based on branch result.

pc + imm

Garcia, FA25

20-Datapath II (23)

The ALU computes PC + Imm

• To compute the address to branch to, use the ALU:

Imm. Gen

inst[31:7]

addr

inst

​

IMEM

Branch Comp.

add

R[rs1]

rdata

addr

DMEM

wdata

clk

clk

clk

alu

R[rs2]

imm[31:0]

pc

+4

mem

alu

inst[31:0]

PCSel

ImmSel

B

RegWEn�

BrUn

BrEq

BrLT

​

BSel

1

ASel

1

MemRW

WBSel

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

1

0

0

1

A

ALU

B

1

0

inst[11:7]

inst[19:15]

inst[24:20]

alu = PC + imm

“select imm”

“select PC”

ALUSel

Add

Imm. Gen

0

1

Garcia, FA25

20-Datapath II (24)

Lighting the Branch Datapath

Imm. Gen

inst[31:7]

addr

inst

​

IMEM

Branch Comp.

add

R[rs1]

rdata

addr

DMEM

wdata

clk

clk

clk

alu

R[rs2]

imm[31:0]

pc

+4

mem

alu

inst[31:0]

PCSel

taken/not taken

BrEq

BrLT

​

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

1

0

0

1

1

0

Imm. Gen

inst[11:7]

inst[19:15]

inst[24:20]

If PCSel=taken, update PC to ALU output. Else, update to next instruction PC + 4.

Build imm from�B-type instruction.

0

1

• Compute branch from R[rs1] and R[rs2]; feed to Control.
• Compute PC + imm.

Don’t write to registers.

A

ALU

B

Don’t write to memory.

(unselected data lines omitted from lighting)

Garcia, FA25

20-Datapath II (25)

The Branch Comparator Block

• The Branch Comparator is a combinational logic block.
• Input:
• Two data busses A and B (datapath�R[rs1] and R[rs2], respectively)
• BrUn (“Branch Unsigned”) control bit
• Control Logic:
• Set BrUn based on current instruction, inst[31:0].
• Set PCSel based on branch flags BrLT, BrEq.

Branch Comp.

R[rs1]

R[rs2]

BrUn

BrEq

BrLT

​

A

​

B

Control Logic

PCSel

taken/not taken

inst[31:0]

• Output:
• BrEq flag: 1 if A == B
• BrLT flag: 1 if A < B.�Unsigned comparison if BrUn=1,�signed otherwise.

[reference]

Garcia, FA25

20-Datapath II (26)

Which Section Should We Discuss?

• Branch Comparator

Agenda

• Adding I-Type
• Implementing Loads
• Implementing Stores
• Adding B-Type (Branches)
• Designing the Immediate Generation Block
• Adding Jumps jal, jalr
• Adding U-Type

Garcia, FA25

20-Datapath II (27)

Garcia, FA25

20-Datapath II (28)

Designing the Immediate Generation Block

Agenda

• Adding I-Type
• Implementing Loads
• Implementing Stores
• Adding B-Type (Branches)
• Designing the Immediate Generation Block
• Adding Jumps jal, jalr
• Adding U-Type

Garcia, FA25

20-Datapath II (29)

Immediate Block? I-Type

inst[31:20]

imm[31:0]

Imm. Gen

Instruction inst[31:0]

Copy upper 12 bits of instruction, inst[31:20], to lower 12 bits of immediate, imm[11:0].

Immediate imm[31:0]

Sign-extend: Copy inst[31] to upper 20 bits of immediate, imm[31:12].

Garcia, FA25

20-Datapath II (30)

I-Type, S-Type Immediates

inst[31:20]

imm[31:0]

Imm. Gen

Immediate imm[31:0]

Instruction inst[31:0]

I-Type

S-Type

Garcia, FA25

20-Datapath II (31)

I-Type, S-Type Immediates

inst[31:20]

imm[31:0]

Imm. Gen

For now, wire instr[31]directly to imm[11] (more next slide).

Sign-extend instr[31] to imm[31:12].

6

Immediate imm[31:0]

Instruction inst[31:0]

I-Type

S-Type

Garcia, FA25

20-Datapath II (32)

B-Type Immediates

inst[31:20]

imm[31:0]

Imm. Gen

I-Type

S-Type

B-Type

instr[31] is always the sign bit.

MUX for imm[11]:

• S: instr[31]
• B: instr[7]

MUX for imm[0]:

• S: instr[7]
• B: 0 (implicit 0;�half-words 🡪 bytes)

Immediate imm[31:0]

Instruction inst[31:0]

Garcia, FA25

20-Datapath II (33)

Adding Jumps jal, jalr

Agenda

• Adding I-Type
• Implementing Loads
• Implementing Stores
• Adding B-Type (Branches)
• Designing the Immediate Generation Block
• Adding Jumps jal, jalr
• Adding U-Type

Garcia, FA25

20-Datapath II (34)

J-Type: Unconditional Jump

• J-Type

BRANCH

• New immediate format!
• State Elements updated:
• PC PC = PC + imm (unconditional PC-relative jump)
• RegFile rd = PC + 4

jal rd, Label

(see Project 3)

Save return address�to RegFile destination register.

Garcia, FA25

20-Datapath II (35)

Block Updates Needed for JAL

Imm. Gen

addr

inst

​

IMEM

Branch Comp.

add

R[rs1]

dataR

addr

DMEM

dataW

clk

clk

alu

R[rs2]

imm[31:0]

pc

+4

mem

pc+4

alu

inst[31:0]

PCSel

�

ImmSel

J

RegWEn

BrUn

BrEq

BrLT

​

BSel

ASel

ALUSel

MemRW

WBSel

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

1

0

0

1

A

ALU

B

0

1

1

0

2

1

0

Immediate Generation Block needs to support J-Types: 20-bit half-words 🡪 byte offset.

inst[11:7]

inst[19:15]

inst[24:20]

inst[31:7]

To save rd = PC + 4, WBSel now controls�a 3-input MUX.

clk

Imm. Gen

WBSel

2

PC = PC + imm

rd = PC + 4

Garcia, FA25

20-Datapath II (36)

Lighting the JAL Datapath

0

1

addr

inst

​

IMEM

Branch Comp.

add

Imm. Gen

0

1

R[rs1]

clk

clk

clk

alu

R[rs2]

imm[31:0]

pc

+4

mem

pc+4

Write PC + 4 to destination register.

2

1

0

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

• Feed PC into blocks.

pc+4

1

0

alu

alu

A

ALU

B

inst[31:0]

BrEq

BrLT

Control Logic

For JAL, “don’t care” about branch.

inst[11:7]

inst[19:15]

inst[24:20]

pc

inst[31:7]

• Write ALU output to PC.

Compute PC + imm.

PC = PC + imm

rd = PC + 4

Don’t write to memory.

Generate byte offset imm for 20-bit PC-relative jump.

(unselected data lines omitted from lighting)

Garcia, FA25

20-Datapath II (37)

I-Type Instruction Layout: jalr

• jalr uses I-Type:

• Two changes to state:
• PC PC = R[rs1] + imm (absolute addressing)
• RegFile R[rd] = PC + 4
• I-Type means jalr uses the same �immediates as arithmetic/loads!
• In other words, imm is already a byte offset.

jalr rd,rs1,imm

Control ImmSel is based on instruction format, not instruction. So far: I,S,B,J

JALR

Garcia, FA25

20-Datapath II (38)

Lighting the JALR Datapath

0

1

addr

inst

​

IMEM

Branch Comp.

add

Imm. Gen

0

1

R[rs1]

clk

clk

clk

alu

R[rs2]

imm[31:0]

pc

+4

mem

pc+4

Write PC + 4 to destination register.

2

1

0

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

Generate 12-bit imm (I-Type).

1

0

alu

alu

A

ALU

B

inst[31:0]

PCSel�taken

BrUn

*

BrEq

BrLT

Control Logic

inst[11:7]

inst[19:15]

inst[24:20]

pc

inst[31:7]

PC = R[rs1] + imm

R[rd] = PC + 4

Don’t write to memory.

Compute�R[rs1] + imm.

• Feed PC into blocks.

• Write ALU output to PC.

(unselected data lines omitted from lighting)

Garcia, FA25

20-Datapath II (39)

Adding U-Types

Agenda

• Adding I-Type
• Implementing Loads
• Implementing Stores
• Adding B-Type (Branches)
• Designing the Immediate Generation Block
• Adding Jumps jal, jalr
• Adding U-Type

Garcia, FA25

20-Datapath II (40)

U-Type Instruction Layout

• “Upper Immediate” instructions:

opname rd,immed

“Destination” Register�

Immediate represents upper 20 bits of a 32-bit immediate imm.

Review

• New immediate format!
• Used for two instructions:
• lui: Load Upper Immediate
• auipc: Add Upper Immediate to PC
• Both increment PC to next instruction and save to destination register.

LUI

AUIPC

(see Project 3)

[reference; see Proj3]

Garcia, FA25

20-Datapath II (41)

U-Type Block update: Immediates

addr

inst

​

IMEM

A

ALU

B

Branch Comp.

add

0

1

R[rs1]

rdata

addr

DMEM

wdata

clk

clk

clk

alu

R[rs2]

imm[31:0]

pc

+4

mem

pc+4

alu

inst[31:0]

ImmSel

U

RegWEn

BrUn

BrEq

BrLT

BSel

ASel

ALUSel

MemRW

Read

WBSel

Control Logic

Generate imm with upper 20 bits. (U-Type)

2

1

0

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

pc+4

1

0

0

1

inst[11:7]

inst[19:15]

inst[24:20]

inst[31:7]

Imm. Gen

PCSel

[reference; see Proj3]

Garcia, FA25

20-Datapath II (42)

Lighting the LUI Datapath

0

1

addr

inst

​

IMEM

A

ALU

B

Branch Comp.

add

R[rs1]

clk

clk

clk

alu

R[rs2]

imm[31:0]

+4

mem

pc+4

alu

inst[31:0]

BrEq

BrLT

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

Grab only imm!�(ALUSel=B)

pc+4

Imm. Gen

2

1

0

1

0

Increment PC to next instruction.

Write result to destination register.

0

1

inst[11:7]

inst[19:15]

inst[24:20]

inst[31:7]

PC = PC + 4

R[rd] = imm

Generate imm with upper 20 bits. (U-Type)

Don’t write to memory.

(unselected data lines omitted from lighting)

Garcia, FA25

20-Datapath II (43)

Lighting the AUIPC Datapath

A

ALU

B

Branch Comp.

add

R[rs1]

clk

clk

clk

alu

R[rs2]

imm[31:0]

+4

mem

pc+4

alu

inst[31:0]

BrEq

BrLT

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

Reg[]

Add PC + imm!

pc+4