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Ali Adib Arnab�Senior Lecturer and Chairman, Department of Electrical and Electronic Engineering�University of Global Village�MSc in Telecommunication and Wireless Systems and Management, Queen Mary University of London

My Google Site Link: https://sites.google.com/view/ali-adib-arnab/home

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Topic 5

Synchronous Sequential Logic

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Latches

  • SR Latch

3

S R

Q

0 0

Q0

0 1

0

1 0

1

1 1

Q=Q’=0

No change

Reset

Set

Invalid

C S R

Q

0 x x

Q0

1 0 0

Q0

1 0 1

0

1 1 0

1

1 1 1

Q=Q’

No change

No change

Reset

Set

Invalid

  • SR Latch with Control Input

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Controlled Latches

  • D Latch (D = Data)

Eastern Mediterranean University

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C D

Q

0 x

Q0

1 0

0

1 1

1

No change

Reset

Set

C

Timing Diagram

D

Q

t

Output may change

D

Q

Q

Q (t+1) = D

When Clock is enabled

Q(t+1) = Q(t)

When Clock is disabled

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Controlled Latches (Task 1)

  • D Latch (D = Data)

Eastern Mediterranean University

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C D

Q

0 x

Q0

1 0

0

1 1

1

No change

Reset

Set

C

Timing Diagram

D

Q

t

Output may change

D

Q

Q

Q (t+1) = D

When Clock is enabled

Q(t+1) = Q(t)

When Clock is disabled

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Controlled Latches

  • D Latch (D = Data)

Eastern Mediterranean University

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C D

Q

0 x

Q0

1 0

0

1 1

1

No change

Reset

Set

C

Timing Diagram

D

Q

Output may change

D

Q

Q

Q (t+1) = D

When Clock is enabled

Q(t+1) = Q(t)

When Clock is disabled

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Flip-Flops

  • T Flip-Flop

Eastern Mediterranean University

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D = TQ’ + T’Q = T Q

J

Q

Q

K

T

D

Q

Q

T

D = JQ’ + K’Q

T

Q

Q

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Flip-Flops

  • Master-Slave D Flip-Flop

Eastern Mediterranean University

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D Latch

(Master)

D

C

Q

D Latch

(Slave)

D

C

Q

Q

D

CLK

CLK

D

QMaster

QSlave

Looks like it is negative edge-triggered

Master

Slave

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Flip-Flops

  • JK Flip-Flop

Eastern Mediterranean University

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J

Q

Q

K

D = JQ’ + K’Q

Q (t+1) = D = JQ’ + K’Q

J

K

Q(t+1)

0

0

Q(t)

0

1

0

1

0

1

1

1

Q’(t)

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Flip-Flop Characteristic Equations

  • Analysis / Derivation

Eastern Mediterranean University

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J

Q

Q

K

J

K

Q(t)

Q(t+1)

0

0

0

0

0

0

1

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

No change

Reset

Set

Toggle

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Flip-Flop Characteristic Equations

  • Analysis / Derivation

Eastern Mediterranean University

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J

Q

Q

K

J

K

Q(t)

Q(t+1)

0

0

0

0

0

0

1

1

0

1

0

0

0

1

1

0

1

0

0

1

0

1

1

1

0

1

1

1

No change

Reset

Set

Toggle

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Flip-Flop Characteristic Equations

  • Analysis / Derivation

Eastern Mediterranean University

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J

Q

Q

K

J

K

Q(t)

Q(t+1)

0

0

0

0

0

0

1

1

0

1

0

0

0

1

1

0

1

0

0

1

1

0

1

1

1

1

0

1

1

1

No change

Reset

Set

Toggle

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Flip-Flop Characteristic Equations

  • Analysis / Derivation

Eastern Mediterranean University

13

J

Q

Q

K

J

K

Q(t)

Q(t+1)

0

0

0

0

0

0

1

1

0

1

0

0

0

1

1

0

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

0

No change

Reset

Set

Toggle

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Mealy and Moore Models

  • The Mealy model: the outputs are functions of both the present state and inputs
    • The outputs may change if the inputs change during the clock pulse period.
      • The outputs may have momentary false values unless the inputs are synchronized with the clocks.
  • The Moore model: the outputs are functions of the present state only.
    • The outputs are synchronous with the clocks.

Eastern Mediterranean University

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Mealy and Moore Models

Eastern Mediterranean University

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Fig. 5.21 Block diagram of Mealy and Moore state machine

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Mealy and Moore Models

Eastern Mediterranean University

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Present State

I/P

Next State

O/P

A

B

x

A

B

y

0

0

0

0

0

0

0

0

1

0

1

0

0

1

0

0

0

1

0

1

1

1

1

0

1

0

0

0

0

1

1

0

1

1

0

0

1

1

0

0

0

1

1

1

1

1

0

0

Mealy

For the same state,�the output changes with the input

Present State

I/P

Next State

O/P

A

B

x

A

B

y

0

0

0

0

0

0

0

0

1

0

1

0

0

1

0

0

1

0

0

1

1

1

0

0

1

0

0

1

0

0

1

0

1

1

1

0

1

1

0

1

1

1

1

1

1

0

0

1

Moore

For the same state,�the output does not change with the input

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Binary Counter Example

  • How about a random number generator.
  • Check the following state diagram and try to identify what it is trying to do :

Eastern Mediterranean University

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Binary Counter Example

  • How about a random number generator.
  • Check the following state diagram and try to identify what it is trying to do :

Eastern Mediterranean University

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Binary Counter Example

  • How about a random number generator.

Eastern Mediterranean University

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Memory Hierarchy

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Registers

  • Group of storage elements read/written as a unit
    • Store related values (e.g. a binary word)
  • Collection of flip-flops with common control
    • Share clock, reset, set lines
  • Example:
    • Storage registers
    • Shift registers
    • Counters

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Storage registers

  • Basic storage registers use flip-flops
  • Example: 4 bit storage register

22

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ROM

23

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ROM

24

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Function table

25

0  0

0   1

0  1

1   0

1  0

1   1

1  1

1   0

F0 (A,B) = A’B+AB’+AB

F1(A,B) = A’B’

22 x 2

ROM

2 bit Input

(Address)

2 bit Output

(Data)

A B F0 F1

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Published Papers��[1] Ali Adib Arnab, Sheikh Sadia Afrin, F.M. Fahad, Hasan U. Zaman, "A cost effective way to build a web controlled search and CO detector rover," DOI:10.1109/CCWC.2017.7868451 (Received the track Best Paper Award), Proceedings of the 7th IEEE Annual Computing and Communication Workshop and Conference (IEEE CCWC 2017), Las Vegas, USA, 9-11 January, 2017, Publisher: IEEE[2] Ali Adib Arnab, Sheikh Md. Razibul Hasan Raj, John Schormans, Sultana Jahan Mukta, Nafi Ahmad "Analysis of the Cost of Varying Levels of User Perceived Quality for Internet Access," https://doi.org/10.1007/978-3-030-68154-8_36 , Proceedings of the 3rd International Conference on Intelligent Computing & Optimization – ICO 2020, Hua Hin, Thailand, 22-23 April, 2021, Publisher: Springer

  • Research and Teaching Interests: 
  • Wireless and Mobile Communication
  • Telecommunication Engineering
  • Communication Theory
  • Electronics
  • Internet of Things
  • Digital Electronics
  • Renewable Energy
  • VLSI