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24EC403 DIGITAL SYSTEM DESIGN �(Lab Integrated)

Department : Electronics and Communication Engineering

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Batch/Year: 2024-2028 / II

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Prepared/Updated by:

Dr.N.KALAIARASI, Professor/RMKEC

Dr.A.MERLINE , Professor/RMKEC

Dr. A. CHILAMBUCHELVAN, Professor/RMDEC

Dr.C.BENNILA THANGAMMAL, Professor/RMDEC

Ms. HEMALATHA , AP/RMDEC

Ms. NISHANTHI K S, AP/RMDEC

Dr.K.G.SHANTHI, Professor/RMKCET

Dr.K.SANGEETHALAKSHMI,ASP/RMKCET

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Date: 3^rd February 2026

Table of Contents

2.COURSE OBJECTIVES

The Course will enable learners to:

• To acquire the knowledge in Digital fundamentals and its

simplification methods.

• To familiarize the design of various combinational digital circuits using logic gates.
• To realize various sequential circuits using flip flops.
• To elucidate various semiconductor memories and related technology.
• To build various logic functions using Programming Logic Devices.

3.PRE REQUISITES

SUBJECT NAME : HSC Physics

4.Syllabus

24EC403

DIGITAL SYSTEM DESIGN

(LAB INTEGRATED)

L T P C 3 0 2 4

UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 9+3

Review of Boolean algebra- theorems, sum of product and product of sum simplification, canonical forms, min term and max term, Simplification of Boolean expressions-Karnaugh map(up to 4 variables), Tabulation Method (up to 4 variables). Implementation of Boolean expressions using logic gates and universal gates.

List of Exercise/Experiments:

1. Implementation of Boolean expression using logic gates.

UNIT II COMBINATIONAL LOGIC CIRCUITS 9+12

Design of combinational circuits - Half and Full Adders, Half and Full Subtractors, Binary Parallel Adder – Carry look ahead Adder, Magnitude Comparator, Decoder, Encoder, Priority Encoder, Mux/De-mux, Parity Generator/Checker, Code converters (Gray to Binary, BCD to Excess-3, vice versa)

List of Exercise/Experiments:

2. Design and verification of adders and subtractors.

3. Design of Multiplexers & Demultiplexers.

4. Design of Encoders and Decoders.

5. Design and verification of code converters(Gray to Binary & Binary to Gray)

UNIT III DESIGN OF SEQUENTIAL CIRCUITS 12+9

Design of clocked sequential circuits - Moore/Mealy models, state minimization, state assignment,circuit implementation. Latches, Flip flops – SR, JK, T, D, Master/Slave FF, Shift Registers - SISO,SIPO, PISO, PIPO. Design and Analysis of synchronous sequential circuits: state table and state diagrams, Design of counters: Modulo-n, Johnson, Ring, Up/Down, Asynchronous counter.

List of Exercise/Experiments:

6. Design and implementation of 3bit ripple counters.

7. Design and implementation of 3bit synchronous counter.

8. Design and implementation of shift registers.

4.Syllabus

24EC403

DIGITAL SYSTEM DESIGN

( LAB INTEGRATED)

L T P C 3 0 2 4

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UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS 6

Stable and Unstable states, output specifications, cycles and races, state reduction, race free assignments, Hazards, Essential Hazards, Design of Hazard free circuits.

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UNIT V MEMORY AND PROGRAMMABLE LOGIC DEVICES 9+6

Basic memory structure ROM: PROM – EPROM – EEPROM –RAM – Static and dynamic RAM – Programmable Logic Devices: Programmable Logic Array (PLA) – Programmable Array Logic (PAL) – Implementation of combinational logic circuits using PLA, PAL.

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List of Experiments:

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9. Implementation of combinational logic circuits using PLA.

10. Implementation of combinational logic circuits using PAL

TOTAL: 45 PERIODS (THEORY) + 30 PERIODS (LAB) = 75 PERIODS

5. Course Outcomes

6. CO – PO /PSO Mapping Matrix

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Total No. of Periods: 9

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7 LECTURE PLAN - UNIT 4: ASYNCHRONOUS SEQUENTIAL CIRCUITS

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8. Activity Based Learning

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Circuit simulator for Asynchronous sequential circuit

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9.Lecture Notes – Unit 4����

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UNIT 4 - Asynchronous Sequential Circuits

Introduction

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A sequential circuit specified by a time sequence of inputs, outputs and internal states. In synchronous sequential circuits. the change of internal state occurs in response to the synchronized clock pulses. Asynchronous sequential circuits do not use clock pulses. The change of internal state occurs when there is a change in the input variables. The memory elements in synchronous sequential circuits are clocked flip-flops. The memory elements in asynchronous sequential circuits are either un clocked flip-flops or time -delay elements. An asynchronous sequential circuit quite often resembles a combinational circuit with feedback.

The design of asynchronous sequential circuits is more difficult than that of synchronous circuits because of the timing problems involved in the feedback path. In a properly designed synchronous system, timing problems are eliminated by triggering all flip-flops with the pulse edge . The change from one state to the next occurs during the short time of the pulse transition. Since the asynchronous circuit does not use a clock. the state of the system m is allowed to change immediately after the input changes. Care must be taken to ensure that each new state keeps the circuit in a stable condition even though a feedback path exists.

Asynchronous sequential circuits are useful in a variety of applications. They are used when speed of operation is important. especially in those cases where the digital system must respond quickly without having to wait for a clock pulse. They are more economical to use in small independent systems that require only a few components, as it may not be practical to go to the expense of providing a circuit for generating clock pulses. Asynchronous circuits are useful in applications where the input signals to the system may change at any time, independently of an internal clock. The communication between two units each having its own independent clock, must be done with asynchronous circuits. Digital designers often produce a mixed system in which some pan of the synchronous system has the characteristics of an asynchronous circuit Knowledge of asynchronous sequential logic behaviour is helpful in verifying that the total digital system is operating in the proper manner.

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Figure shows the block diagram of an asynchronous sequential circuit that consists of a combinational circuit and de lay elements connected to form feedback loops. There are n input variables, m output variables, and k internal states. The delay elements can be visualized as providing short-term memory for the sequential circuit. In a gate-type circuit, the propagation delay that exists in the combinational circuit path from input to output provides sufficient delay along the feedback loop so that no specific delay elements are actually inserted into the feedback path. The present-state and next-state variables in asynchronous sequential circuits are customarily called secondary variables and excitation variables, respectively. When an input variable changes in value, the y secondary variables do not change instantaneously. Note the distinction between the y's and the Y’s.

In the steady-state condition, they are the same, but during transition they are not. For a given value of input variables. the system is stable if the circuit reaches a steady-state condition with Yi = Y; for i = 1. 2, . . . • k. To ensure proper operation, asynchronous sequential circuits must be allowed to attain a stable state before the input is changed to a new value. Because of delays in the wires and the gate circuits, it is impossible to have two or more input variables change at exactly the same instant of time without an uncertainty as to which one changes first. Therefore , simultaneous changes of two or more variables are usually prohibited. This restriction means that only one input variable can change at anyone time and the time between two input changes must be longer than the time it lakes the circuit to reach a stable state. Such operation, defined as fundamental mode. Assumes that the input signals change one at a time and only when the circuit is in a stable condition.

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Stable-Unstable state -Stability considerations

Why Asynchronous Circuits?

Because of the feedback connection that exists in asynchronous sequential circuits, care must be taken to ensure that the circuit does not become unstable. An unstable condition will cause the circuit to oscillate between unstable states. The transition-table method of analysis can be useful in detecting the occurrence of instability.

Consider, for example the circuit of Fig (a). The excitation function is

The transition table for the circuit is shown in Fig. (b). Those values of Y which are equal to y are circled and represent stable states. Uncircled entries indicate unstable conditions. Note that column 11 has no stable stales. This means that with input X1X2 fixed at 11. the values of Y and y are never the same.

If y = O. then Y = I. which causes a transition to the second row of the table. with y = 1 and Y = O. This in tum causes a transition back to the first row with the result that the state variable alternates between 0 and 1 indefinitely, as long as the input is 11 .

The instability condition can be detected directly from the logic diagram .

Asynchronous sequential circuits- analysis procedure

The analysis of asynchronous sequential circuits proceeds in much the same way as that of clocked synchronous sequential circuits. From a logic diagram, Boolean expressions are written and then transferred into tabular form.

The analysis procedure will be presented by means of three specific examples. The first example introduces the transition table, the second defines the flow table , and the third investigates the stability of asynchronous sequential circuits.

An example of an asynchronous sequential circuit with only gates is shown in Fig. The diagram clearly shows two feedback loops from the OR gate outputs back to the AND gate inputs. The circuit consists of one input variable x and two internal states. The internal states have two excitation variables, Y1 and Y2 and two secondary variables, Y1 and Y2. The delay associated with each feedback loop is obtained from the propagation delay between each Y input and its corresponding y output. Each logic gate in the path introduces a propagation delay of about 2 to 10ns. The wires that conduct electrical signals introduce approximately a 1ns delay for each foot of wire. Thus, no additional external delay elements are necessary when the combinational circuit and the wires in the feedback path provide sufficient delay.

The analysis of the circuit starts with a consideration of the excitation variables as outputs and the secondary variables as inputs. We then derive the Boolean expressions for the excitation variables as a function of the input and secondary variables. These expressions readily obtained from the logic diagram are

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Asynchronous sequential circuits- analysis procedure

The next step is to plot the Y1 and Y2 functions in a map as shown in Fig. (a) and (b).

The encoded binary values of the y variables are used for labeling the rows and the input x variable is used to designate the columns. This configuration results in a slightly different three variable map.

Combining the binary values in corresponding squares the following transition table is obtained.

The transition table shows the value of Y = Y₁Y₂ inside each square. Those entries where Y = y are circled to indicate a stable condition.

The circuit has four stable total states Y₁Y₂ x = 000, 011, 110, and 101 - and four unstable total states - 001, 010, 111, and 100.

The procedure for obtaining a transition table from the circuit diagram of an asynchronous sequential circuit is as follows

1. Determine all feedback loops in the circuit.
2. Designate the output of each feedback loop with variable Yi; and its corresponding input with Yi for i = 1,2,... k, where k is the number of feedback loops in the circuit.
3. Derive the Boolean functions of all Y's as a function of the external inputs.
4. Plot each Y function in a map, using the y variables for the rows and the external inputs for the columns.
5. Combine all the maps into one table showing the value of Y = Y1Y2 ••• Yk inside each square.
6. Circle those values of Y in each square that are equal to the value of y

=“y1,y2…yk" in the same row. Once the transition table is available, the

behavior of the circuit can be analyzed by observing the stale transition as a function of changes in the input variables.

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Output Specifications

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Asynchronous sequential circuits- analysis procedure

Flow table

During the design of asynchronous sequential circuits, it is more convenient to name the states by letter symbols without making specific reference to their binary values. Such a table is called a flow table and is similar to a transition table, except that the internal states are symbolized with letters rather than binary numbers.

The flow table also includes the output values of the circuit for each stable state.

Examples of flow tables are shown in Fig. The Fig. (a) has four states designated by the letters a, b, c and d. It reduces to the transition table of Fig. (c ) if we assign the following binary values to the states: a = 00. b = 0 I. c = 11 and d = 10.

The table of Fig (a) is called a primitive flow table because it has only one stable state in each row. Figure (b) shows a flow table with more than one stable in a same row .

In order to obtain the circuit described by a flow table, it is necessary to assign to each state a distinct value. This assignment converts the flow table into a transition table. This is shown below:

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The resulting logic diagram is shown below:

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Cycles and Races

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A race condition exists in an asynchronous circuit when two or more binary state variables change value in response to a change in an input variable. When unequal delays are encountered, a race condition may cause the state variable to change in an unpredictable manner.

If the final stable state that the circuit reaches does not depend on the order in which the state variables change, the race is called a non critical race. Examples of non critical races are illustrated in the transition tables below:

A critical race condition occurs when the order in which internal variables are

changed determines the eventual state that the state machine will end up in.

The transition tables below illustrate critical races:

Races can be avoided by directing the circuit through a unique sequence of intermediate unstable states. When a circuit does that, it is said to have a cycle.

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Again, we start with y1y2 = 00 and change the input from 0 to 1. The transition table of part (a) give s a unique sequence that terminates in a total stable state 101.

The table in (b) shows that even though the state variables change from 00 to 11. The cycle provides a unique transition from 00 to 0 1 and then to 11. Care must betaken when using a cycle that terminates with a stable state. If a cycle does not terminate with a stable state, the circuit will keep going from one unstable state to another, making the entire circuit unstable. This phenomenon is demonstrated in Fig and also in the next example.

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Analysis Example

The first step is to obtain the Boolean functions for the S and R inputs in each latch:

We then check whether the condition SR = 0 is satisfied to ensure proper operation of the circuit :

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The result is 0 because x₁x₁’ = X₂ X₂’ = 0.

The next step is to derive the transition table of the circuit. Remember that the transition table specifies the value of Y as a function of y and x . The excitation functions are derived from the relation Y = S + R’ y

We now develop a composite map for Y = Y1 Y2.The y variables are assigned to the rows in the map, and the x variables are assigned to the columns , as shown in Fig. The Boolean functions Y1 and Y2. as just expressed are used to plot the composite map for Y.

The entries of Y in each row that have the same value as that given to y are circled and represent stable states. Investigating the transition table, we deduce that the circuit is stable. There is a critical race condition when the circuit is initially in total state Y1Y2X1X2 = 1101( Y1Y2 = 11) and X2 changes from 1 to O (Y1Y2 = 00). If Y1 changes to 0 before Y2, the circuit goes to total state 0100 instead of 0000. However, with approximately equal delays in the gates and latches, this undesirable situation is not likely to occur.

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The procedure for analyzing an asynchronous sequential circuit with SR latches can be summarized as follows:

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State Reduction

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Design procedure-asynchronous sequential circuit

There are a number of steps that must be carried out in order to minimize the circuit complexity and to produce a stable circuit without critical races. Briefly, the design steps are as follows:

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1. Obtain a primitive flow table from the given specification.
2. Reduce the flow table by merging rows in the primitive flow table
3. Assign binary states variables to each row of the reduced flow table to obtain the transition table.
4. Assign output values to the dashes associated with the unstable states to obtain the output maps.
5. Simplify the Boolean functions of the excitation and output variables and draw the logic diagram.

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Problem :

Design a gated latch circuit with two inputs, G (gate) and D (data), and one output

Q. The gated latch is a memory element that accepts the value of D when G = 1 and retains this value after G goes to 0. Once G = 0, a change in D does not change the value of the output Q.

Step 1: Primitive Flow Table:

A primitive flow table is a flow table with only one stable total state in each row. The total state consists of the internal state combined with the input.

To derive the primitive flow table, first a table with all possible total states in the

system is needed:

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The resulting primitive table for the gated latch is shown below:

First, we fill in one square in each row belonging to the stable state in that row.

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• Next recalling that both inputs are not allowed to change at the same time, we enter dash marks in each row that differs in two or more variables from the input variables associated with the stable state.

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• Next we find values for two more squares in each row. The comments listed in the previous table may help in deriving the necessary information. A dash indicates don’t care conditions.

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Step 2: Reduction of the Primitive Flow Table

The primitive flow table can be reduced to a smaller number of rows if two or more stable states are placed in the same row of the flow table. The simplified merging rules are as follows:

1. Two or more rows in the primitive flow table can be merged into one if there

are nonconflicting states and outputs in each of the columns.

2. Whenever, one state symbol and don’t care entries are encountered in the same column, the state is listed in the merged row.

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3. If the state is circled in one of the rows, it is also circled in the merged row.
4. The output state is included with each stable state in the merged row. Now

apply these rules to the primitive flow table shown previously.

To see how this is done the primitive flow table is separated into two parts of three rows each:

Each part shows three stable states that can be merged because there no conflicting entries in each of the four columns. Since a dash represents a don’t care condition it can be associated with any state or output. The first column of can be merged into a stable state c with output 0, the second into a stable state a with output 0, etc.

The resulting reduced flow table is as follows:

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Step 3: Transition Table and Logic Diagram

• To obtain the circuit described by the reduced flow table, a binary value must be assigned to each state. This converts the flow table to a transition table.
• In assigning binary states, care must be taken to ensure that the circuit will be free of critical races. No critical races can occur in a two-row flow table.
• Assigning 0 to state a and 1 to state b in the reduced flow table, the following transition table is obtained:

The transition table is, in effect, a map for the excitation variable Y. The simplified Boolean function for Y as obtained from the map is:

Y = DG +G′’y

There are two don’t care outputs in the final reduced flow table. By assigning values to the output as shown below:

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There are two don’t care outputs in the final reduced flow table. By assigning values

to the output as shown below:

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It is possible to make output Q equal to Y. If the other possible values are assigned to the don’t care outputs, output Q is made equal to y. In either case, the logic diagram of the gated latch is as follows:

Step 4 :Reduction of state and flow tables

The procedure for reducing the number of internal states in an asynchronous sequential circuit resembles the procedure that is used for synchronous circuits.

Implication Table

The state-reduction procedure for completely specified state tables is based on the algorithm that two states in a state table can be combined into one if they can be shown to be equivalent.

There are occasions when a pair of states do not have the same next states, but,

nonetheless, go to equivalent next states.

Consider the following state table:

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(a, b) imply (c, d) and (c, d) imply (a, b). Both pairs of states are equivalent; i.e., a and b are equivalent as well as c and d.

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The checking of each pair of states for possible equivalence in a table with a large number of states can be done systematically by means of an implication table. This a chart that consists of squares, one for every possible pair of states, that provide spaces for listing any possible implied states.

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Consider the following state table

The implication table is:

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• On the left side along the vertical are listed all the states defined in the state table except the last, and across the bottom horizontally are listed all the states except the last .

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• The states that are not equivalent are marked with a ‘x’ in the

corresponding square, whereas their equivalence is recorded with a ‘√’.

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• Some of the squares have entries of implied states that must be further investigated to determine whether they are equivalent or not.
• The step-by-step procedure of filling in the squares is as follows:
• Place a cross in any square corresponding to a pair of states whose outputs are not equal for every input.
• Enter in the remaining squares the pairs of states that are implied by the pair of states representing the squares. We do that by starting from the top square in the left column and going down and then proceeding with the next column to the right.
• Make successive passes through the table to determine whether any additional squares should be marked with a ‘x’. A square in the table is crossed out if it contains at least one implied pair that is not equivalent.
• Finally, all the squares that have no crosses are recorded with check marks. The equivalent states are: (a, b), (d, e), (d, g), (e, g).

We now combine pairs of states into larger groups of equivalent states. The last three pairs can be combined into a set of three equivalent states (d, e, g) because each one of the states in the group is equivalent to the other two. The final partition of these states consists of the equivalent states found from the implication table, together with all the remaining states in the state table that are not equivalent to any other state:

(a, b) (c) (d, e, g) (f)

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The reduced state table is:

Step 5:Merging of the Flow Table

There are occasions when the state table for a sequential circuit is incompletely specified.

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Incompletely specified states can be combined to reduce the number of states in the flow table. Such states cannot be called equivalent, but, instead they are said to be compatible.

The process that must be applied in order to find a suitable group of compatibles for the purpose of merging a flow table is divided into three steps:

1. Determine all compatible pairs by using the implication table.
2. Find the maximal compatibles using a merger diagram.
3. Find a minimal collection of compatibles that covers all the states and is closed.

We will now proceed to show and explain the three procedural steps using the following primitive flow table:

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Compatible Pairs

Two states are compatible if in every column of the corresponding rows in the flow table, they are identical or compatible states and if there is no conflict in the output values. The compatible pairs (√) are: (a, b) (a, c) (a, d) (b, e) (b, f) (c, d) (e, f)

Maximal Compatibles

The maximal compatible is a group of compatibles that contains all the possible combinations of compatible states. The maximal compatible can be obtained from a merger diagram:

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The above merger diagram is obtained from the list of compatible pairs derived from the previous implication table. A line represents a compatible pair. A triangle constitutes a compatible with three states. The maximal compatibles are: (a, b) (a, c, d) (b, e, f) .

In the case where a state is not compatible to any other state, an isolated dot represents this state.

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Race-Free State Assignment

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• Once a reduced flow table has been derived for an asynchronous sequential circuit, the next step in the design is to assign binary variables to each stable state. This assignment results in the transformation of the flow table into its equivalent transition table.
• The primary objective in choosing a proper binary state assignment is the prevention of critical races. Critical races can be avoided by making a binary state assignment in such a way that only one variable changes at any given time when a state transition occurs in the flow table.

Three-Row Flow-Table Example

• To avoid critical races, we must find a binary state assignment such

that only one binary variable changes during each state transition.

• An attempt to find such an assignment is shown in the transition diagram.
• State a is assigned binary 00, and state c is assigned binary 11.
• This assignment will ca use a critical race during the transition from a to c because there are two changes in the binary state variables and the transition from a to c may occur directly or pass through b.
• Note that the transition from c to a also ca uses a race condition, but it is noncritical because the transition does not pass through other states.
• A race-free assignment can be obtained if we add an extra row to the flow table. The use of a fourth row does not increase the number of binary state variables, but it allows the formation of cycles between two stable states.
• The transition table corresponding to the flow table with the indicated binary state assignment is shown in Fig. The two dashes in row d represent unspecified states that can be considered don't- care conditions. However, care must be taken not to assign 10 to these squares, in order to avoid the possibility of an unwanted stable state being established in the fourth row.

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Four-Row Flow-Table Example

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A flow table with four rows requires a minimum of two state variables. Although a race- free assignment is sometimes possible with only two binary state variables, in many cases the requirement of extra rows to avoid critical races will dictate the use of three binary state variables

Fig: Four-row flow-table example

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The following figure shows a state assignment map that is suitable for any four-row flow table. States a, b, c and d are the original states and e, f and g are extra states.

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The transition from a to d must be directed through the extra state e to produce a cycle so that only one binary variable changes at a time.

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Similarly, the transition from c to a is directed through g and the transition from d to c goes through f. By using the assignment given by the map, the four-row table can be expanded to a seven-row table that is free of critical races.

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State assignment to modified flow table

Fig. State assignment to modified flow table

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Note that although the flow table has seven rows there are only four stable states. The uncircled states in the three extra rows are there merely to provide a race-free transition between the stable states.

Toproduce cycles:

The transition from a to d must be directed through the extra state e.

The transition from c to a must be directed through the extra state g. The transition from d to c must be directed through the extra state f.

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Multiple-Row Method

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The method for making race-free stale assignments by adding extra rows in the flow table is referred to as the shared-row method.

• A second method called the multiple-row method is not as efficient, but is easier to apply.
• In multiple- row assignment each state in the original row table is replaced by two or more combinations of state variables.

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Multiple-Row Method

• There are two binary state variables for each stable state, each variable being the logical complement of the other. For example, the original state a is replaced with two equivalent states a1 =000 and a2 = 111.
• The output values, not shown here must be the same in a1 and a2. Note that a1 is adjacent to b1, c2 and d1, and a2 is adjacent to c1, b2 and d2, and similarly each state is adjacent to three states with different letter designations.
• The expanded table is formed by replacing each row of the original table with two rows. In the multiple-row assignment, the change from one stable state 10 another will always cause a change of only one binary state variable.
• Each stable stale has two binary assignments with exactly the same output.

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Hazards

In designing asynchronous sequential circuits, care must be taken to conform with certain restrictions and precautions to ensure that the circuits operate properly.

The circuit must be operated in fundamental mode with only one input changing at any time and must be free of critical races.

In addition, there is one more phenomenon called a hazard, that may cause the circuit to malfunction.

Hazards are unwanted switching transients that may appear at the output of a circuit because different paths exhibit different propagation delays.

Hazard s occur in combinational circuits, where they may cause a temporary false

output value.

When they occur in asynchronous sequential circuits. hazards may result in a transition to a wrong stable stare. It is there fore necessary to check for possible hazards and determine whether they can cause improper operations. If so, then steps must be taken to eliminate their effect.

Hazards In Combinational Circuits

A hazard is a condition in which a change in a single variable produces a momentary change in output when no change in output should occur.

The circuit of Fig.(a) depicts the occurrence of a hazard. Assume that all three inputs are initially equal to 1. This causes the output of gate 1 to be 1, that of gate 2 to be 0. and that of the circuit to be 1. Now consider a change in x ₂ from 1 to 0. Then the output of gale 1 changes to 0 and that of gate 2 changes to 1, leaving the output at 1.

However, the output may momentarily go to 0 if the propagation delay through the inverter is taken into consideration. The delay in the inverter may cause the output of gate 1 to change to 0 before the output of gale 2 changes to 1. In that case, both inputs of gate 3 are momentarily equal to 0 causing the output to go to 0 for the short time during which the input signal from X₂ is delayed while it is propagating through the Inverter circuit.

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Design of Hazards free circuit

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The circuit of Fig.(b) is a NAND implementation of the Boolean function in Fig.(a)and it has a hazard for the same reason. Because gates 1 and 2 are NAND gates ,their outputs are the complement of the outputs of the corresponding AND gates. When X₂ changes from 1 to 0, both inputs of gate 3 may be equal to 1 causing the output to produce a momentary change to 0 when it should have stayed at 1.

The two circuits shown in Fig. implement the Boolean function in sum-of-products

form Y=x₁x₂+x₂’x₃

This type of implementation may cause the output to go to 0 when it should remain at 1. If however, the circuit is implemented instead in product-of-sums form namely

Y=(x₁+x₂’)(x₂+x₃)

then the output may momentarily go to 1 when it should remain 0.The first case is referred to as static 1-hazard and the second case as static 0-hazard.

A third type of hazard, known as dynamic hazard, causes the output to change three or more times when it should change from 1 to 0 or from 0 to 1. Figure. illustrates the three types of hazards.

When a circuit is implemented in sum-of-products form with AND-OR gates or with NAND gates, the removal of static 1-hazard guarantees that no static 0-hazards or dynamic hazards will occur. A hazard can be detected by inspection of the map of the particular circuit. To illustrate, consider the map in Fig.(a) which is a plot of the function implemented in Fig. The change in X₂ from 1 to 0 moves the circuit from minterm 111 to minterm 101.The hazard exists because the change in input results in a different product term covering the two minterms.

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Essential Hazards

Minterm 111 is covered by the product term implemented in gate 1 of Fig and minterm 101 is covered by the product term implemented in gate 2. Whenever the circuit must move from one product term to another. there is a possibility of a momentary interval when neither term is equal to 1 , giving rise to an undesirable 0 output. The remedy for eliminating a hazard is to enclose the two minterms in question with another product term that overlaps both groupings. This situation is shown in the map of Fig. (b).

where the two minterms that cause the hazard are combined into one product term. The hazard-free circuit obtained by such a configuration is shown ,the extra gate in the circuit generates the product term . In general, hazards in combinational circuits can be removed by covering any two minterms that may produce a hazard with a product term common to both. The removal of hazards requires the addition of redundant gates to the circuit.

Hazards in asynchronous circuit

In normal combinational-circuit design associated with synchronous sequential circuits. Hazards are of no concern, since momentary erroneous signals are not generally troublesome . However, if a momentary incorrect signal is fed back in an asynchronous sequential circuit, it may cause the circuit to go to the wrong stable state. This situation is illustrated in Fig.

If the circuit is in total stable state yx1 x2 = 111 and input x2 changes from 1 to 0, the next total stable state should be 110. However. because of the hazard, output Y may go to 0 momentarily. If this false signal feeds back into gate 2 before the output of the inverter goes to 1. the output of gate 2 will remain at 0 and the circuit will switch to the incorrect total stable stale 010. This malfunction can be eliminated by adding an extra gate , as is done in Fig.

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Essential Hazards

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An essential hazard is the result of the effects of a single input variable change reaching one feedback path before another feedback path.

Essential hazards cannot be corrected by adding redundant gates as in static

hazards.

They can always be eliminated in a realization by the insertion of sufficient delays in the feedback paths. Facility in doing this comes only with experience.

Remove Hazards with Latches

Implement the asynchronous circuit with SR latches can also remove static hazards

A momentary 0 has no effects to the S and R inputs of a NOR latch

A momentary 1 has no effects to the S and R inputs of a NANDlatch

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Pulse mode Asynchronous sequential circuits

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Design an asynchronous sequential circuit that has two inputs and one output Z. When , the output Z is 0.The first change in that occurs while is 1 will cause output Z to be 1. The output Z will remain 1 until returns to 0.

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Links to Videos and Learning Materials

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10. ASSIGNMENT

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11: Part-A: Q & A

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12: Part-B: Questions

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13 Supportive online Certification courses

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14 Real time Applications in day to day life and to

Industry

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Asynchronous CPUs are one of several ideas for radically changing CPU design.

Unlike a conventional processor, a clockless processor (asynchronous CPU) has no central clock to coordinate the progress of data through the pipeline. Instead, stages of the CPU are coordinated using logic devices called "pipeline controls" or "FIFO sequencers." Basically, the pipeline controller clocks the next stage of logic when the existing stage is complete. In this way, a central clock is unnecessary. It may actually be even easier to implement high performance devices in asynchronous, as opposed to clocked, logic: components can run at different speeds on an asynchronous CPU; all major components of a clocked CPU must remain synchronized with the central clock; a traditional CPU cannot "go faster" than the expected worst-case performance of the slowest stage/instruction/component. When an asynchronous CPU completes an operation more quickly than anticipated, the next stage can immediately begin processing the results, rather than waiting for synchronization with a central clock. An operation might finish faster than normal because of attributes of the data being processed (e.g., multiplication can be very fast when multiplying by 0 or 1, even when running code produced by a naive compiler), or because of the presence of a higher voltage or bus speed setting, or a lower ambient temperature, than 'normal' or expected. Asynchronous logic proponents believe these capabilities would have these benefits: lower power dissipation for a given performance level, and highest possible execution speeds.

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In 2004, Epson manufactured the world's first bendable microprocessor called ACT11, an 8-bit asynchronous chip. Synchronous flexible processors are slower, since bending the material on which a chip is fabricated causes wild and unpredictable variations in the delays of various transistors, for which worst-case scenarios must be assumed everywhere and everything must be clocked at worst- case speed. The processor is intended for use in smart cards, whose chips are currently limited in size to those small enough that they can remain perfectly rigid.

In 2014, IBM announced a SyNAPSE-developed chip that runs in an asynchronous manner, with one of the highest transistor counts of any chip ever produced. IBM's chip consumes orders of magnitude less power than traditional computing systems on pattern recognition benchmarks

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15: Self-Learning / Enrichment Topics

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Fundamental Mode Asynchronous Circuits

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The fundamental mode asynchronous circuit design is based on the following

assumptions :

1. The inputs (I) to the synchronous circuits change only when the circuit is stable, that means when the state variables (S) are not in their transition state.
2. Another assumption is that the inputs are levels and not pulses.
3. The state variables in these circuits are characterized as delay elements. Delay may be introduced by a latch or simply the propagation delay inherent in the logic gates used for realizing the asynchronous circuits.

Total state :

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The behavior of an asynchronous machine is determined by defining the total state.

The total state is divided into two parts.

• The input state (I).
• The internal or secondary state (value of S).

Thus the total state is defined by the value of (I, S). The total state can be either stable or unstable.

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Stable total state :

• A stable total state is defined as the state which produces no additional state transitions. If I does not change then (I, S) remains stable.

A total state transition occurs when a given input state (I) causes the excitation of memory to produce a secondary state (S).

The secondary state outputs (S) are applied to the output logic (p) as well as to the input (f) to produce the memory excitation inputs (E).

When the inputs to the combinational excitation logic do not produce any new values for the secondary states (S) the machine is said to be stable.

The time delay required to reach the stable state depends on the following factors:

• Excitation.
• Memory logic delays and
• State assignment.

A large number of secondary state changes could occur before the machine reaches a stable total state. Note that in the fundamental mode model, the input state (I) is not allowed to change until the circuit has reached a stable total state. This is because if changes in (I) were allowed before a total stable state were reached, then the circuit may never reach a stable condition at all. One more important requirement of the fundamental mode asynchronous machine is that only one input variable can change at a given time. If this requirement is not satisfied, then the asynchronous circuit can make erroneous total state transitions.

16.Assessment Schedule (Proposed Date & Actual Date)

17.Prescribed Text Books & References

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TEXT BOOK:

1. M. Morris Mano and Michael D. Ciletti, Digital Design, With an Introduction to the

Verilog HDL, VHDL, and System Verilog, 6^th Edition, Pearson, 2018.

2. S.Salivahanan and S.Arivazhagan,Digital Circuits and Design, 5^th Edition, Oxford University Press, 2018.

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REFERENCES:

1. A.Anandkumar, Fundamental of digital circuits, 4^th Edition, PHI Publication,2016.
2. William Kleitz, Digital Electronics-A Practical approach to VHDL, Prentice Hall International Inc, 2012.
3. Charles H.Roth, Jr. andLarry L. Kinney, Fundamentals of Logic Design, 7^th Edition, Thomson Learning, 2014.
4. Thomas L. Floyd, Digital Fundamentals, 11^th Edition, Pearson Education Inc, 2017.
5. John.M Yarbrough, Digital Logic: Applications and Design, 1^st Edition, Cengage India, 2006.

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NPTEL LINK: https://nptel.ac.in/courses/108/105/108105132/

18. Mini Projects/ Activity

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1. Gaming control

Many game shows use a circuit to determine which of the contestants ring in first. Design a circuit to determine which of two contestants rings in first. It has two inputs S1 and S0 which are connected to the contestants' buttons. The circuit has two outputs Z1 and Z0 which are connected to LED's to indicate which contestant rang in first. There is also a reset button that is used by the game show host to asynchronously reset the flip-flops to the initial state before each question. If contestant 0 rings in first, the circuit turns on LED 0. Once LED 0 is on, the circuit leaves it on regardless of the inputs until the circuit is asynchronously reset by the game show host. If contestant 1 rings in first, the circuit turns on LED 1 and leaves it on until the circuit is reset. If there is a tie, both LED's are turned on. The circuit requires four states: reset, contestant 0 wins, contestant 1 wins, and tie. One way to map the states is to use state 00 for reset, state 01 for contestant 0 wins, state 10 for contestant 1 wins, and state 11 for a tie. With this mapping, the outputs are equal to the current state, which simplifies the output equations.

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2. Traffic light controller

Design a simplified traffic-light controller that switches traffic lights on a crossing where a north-south (NS) street intersects an east-west (EW) street. The input to the controller is the WALK button pushed by pedestrians who want to cross the street. The outputs are two signals NS and EW that control the traffic lights in the Ns and EW directions. When NS or EW are 0, the red light is on, and when they are 1, the green light is on. When there are no pedestrians, NS=0, EW=1 for a minute, follow by NS=1 and EW=0 for 1 minutes, and so on, when WALK button is pushed, Ns and EW both become 0 for a minute when the present minute expires. After that the NS and EW signals continue alerting. For this traffic-light controller: a) Develop a state diagram. (Hint: can be done using 3 states) b) Draw the state transition table. c) Encode the states using minimum number of bits. d) Derive the logic schematic for a sequential circuit which implements the state transition table.

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3. Bidirectional Visitor Counter

Display the number of students in the class. Whenever a student enters the class, an upcounter is activated and the display increases by 1. Whenever a student leaves the class, a down counter is activated and the display decreases by 1.

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4. Count the number of cars in a parking lot

Display the number of cars in the parking lot. Whenever a car enters the parking lot, an upcounter is activated and the display increases by 1. Whenever a car leaves the parking lot, a down counter is activated and the display decreases by 1.

5. Automatic Washroom Light Switch

(https://www.electronicshub.org/automatic-washroom-light-switch/)

The reed switch is fixed to the wall near the door while the magnet is fixed to the door. This means that the reed switch will always be in closed state as the door is closed when the washroom is not in use (which is assumed as starting point) and the magnet will be near the switch. When the door is opened and then closed the door, this action will make the switch open (when the door is opened first) and close (when you close the door). As a result, the output of the Op-amp goes HIGH (when open the door) and then goes LOW (when close the door). This in turn will cause the counter to produce a HIGH output at its Pin 2. Since Pin 2 of CD4017 is connected to the relay, the light will be turned ON. While coming out, the door is once again opened and closed. This action will once again cause the same action i.e. switch will open and close and output of Op-Amp will become HIGH and then LOW. But, since the Pin 4 of CD4017 is connected to the Reset pin, all the outputs will become LOW and hence the relay will be turned OFF, which in turn switches off the light.

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6. Dancing LEDs

A group of 10 LEDs is connected to a 10 bit shift register. Whichever LED has to glow, then send 1 for others 0. Thus by sending different combinations of 1’s and 0’s the LEDs are made to glow in different fashion making them to dance.

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7. Digital Alarm

The clock is given in such a way that the 4 bit counter increases its count after 1 sec. After the counter counts 10, the buzzer will give alarm sound. Thus it produces a 10 sec alarm

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8. Design a traffic light

A traffic light is installed at a junction of a railroad and a road. The light is controlled by two switches in the rails placed 1 mile apart on either side of the junction. A switch is turned on when the train is over it and is turned off otherwise. The traffic light changes from green (logic 0) to red (logic 1) when the beginning of the train is 1 mile from the junction. The light changes back to green when the end of the train is 1 mile away from the junction. Assume that the length of the train is less then 2 miles. Obtain a primitive flow table for the circuit. Show that the flow table can be reduced to four rows. With further procedures implement the same.

9. 12-Hour Clock

Digital clocks are usually set up to start at 12:00, and they count 12:01, 12:02, 12:03, 12:04, 12:05, 12:06, 12:07, 12:08, 12:09, 12:10, and eventually the clock gets to 12:58, 12:59, 1:00, and so on. The one's place of the minutes (the right-most digit) counts 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, and then repeats, and a circuit that counts in this way is called a mod-10 counter. The ten's place of the minutes (second digit from the right) counts 0, 1, 2, 3, 4, 5, and then repeats, which is called a mod-6 counter. The hour counter counts 12, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and repeats. The output from each counter is a binary coded decimal (BCD) number that represents one of the digits in the time, and BCD-to-Seven segment decoders are used to drive the seven segment displays

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GATE QUESTIONS

1. Consider the given circuit. In this circuit, the race around

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1. does not occu
2. Occurs when Clk = 0
3. Occurs when Clk = 1, A=B=0
4. Occurs when Clk = 1, A=B=1

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2. When the output Y in the circuit below is ‘1’, it implies that data has

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1. changed from 0 to 1
2. changed form 1 to 0
3. changed in either direction
4. not changed

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3. Figure shows a mod-K counter, Here K is equal to

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1. 1
2. 2
3. 3
4. 4

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Thank you

Disclaimer:

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