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PUNCHY - Not Tooooooooooo Long �Super Cool Title

Your Name, …, David Atienza

EPFL - Embedded Systems Laboratory

your.email@epfl.ch

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Outline

  • Intro
    • Motivation
    • Background
    • Challenges
  • Topic 1
    • High throughput requirements
    • Scalability
  • Topic 2
    • Energy-efficient HPC
  • Results
  • Discussion

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ESL in a nutshell

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Embedded systems and computer engineering

    • Wearables and Internet-of-Things (IoT)
    • Low-power hardware-software co-design
    • System-level design methodologies for HPC

14 years at EPFL, 48 members today

    • 8 post-docs (17 so far, 10 moved to industry)
    • 30 PhD students (21 already graduated)

Innovation and tech. transfer: basic and applied research

    • 31 companies provided grants and donations

Intro

Topic 1

Topic 2

Results

Discussion

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Motivation for sustainable acceleration

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Context

    • SKAO will operate for 50+ years
    • Sustainability goals: SDP < 1 MWatt
    • Science goals: high throughput req.

Challenge

    • Plan and design energy efficient data centers
    • Software pipeline not fixed and evolving

Solution

    • HW-SW codesign
    • Heterogeneous computing
    • Reconfigurable accelerators

Intro

Topic 1

Topic 2

Results

Discussion

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Motivation

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    • Energy efficient ….

Knowledge gap

    • …..
    • ….

Proposal

Intro

Topic 1

Topic 2

Results

Discussion

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Tradeoffs: Programmability vs Energy Efficiency

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DSIP

GPP

ASIP

Energy

Efficiency

(MOPS/mW)

ASIC

FPGA

GPU

DSP

CPU

CGRAlike

1000

100

10

1

Flexibility (Programming)

Adapted from Kevin J M Martin. IPDPSW 2022

Near-fixed

Low-level programming

High-level programming

ASIP: Application Specific Instruction Processor

DSIP: Domain Specific Instruction-set Processor

GPP: General Purpose Processor

Intro

Topic 1

Topic 2

Results

Discussion

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Quest for green acceleration: HW-SW codesign

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3 paths HW-SW codesign, given starting point

    • Only specifications - open choice for a model
    • Existing software implementation
    • Existing hardware (chip – CPU, GPU)

​

System specification

Hardware functionality

Hardware architecture

Software requirements

Software Design

& Test

System integration

Integrated modelling

Incremental evaluation

Verification & validation

We only have pieces of the puzzle from each

Intro

Topic 1

Topic 2

Results

Discussion

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Software: Imaging Pipeline Bottleneck

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Convolutional Gridding

iFFT

Minor Cycle

50-500x iter

~10Gb/s

Apply Gains�Gain Subtraction

Deconvolution, FFT (CLEAN)

Major Cycle

8-30x iterations

~7Tb/s

~100Pflop

Visibilities �

Residual Image of the Sky

FFT

Degridding

Visibility domain

Image domain

Numbers based on MeerKAT

– precursor of SKA Mid, Karoo desert

Sky

model

Restore clean image

Intro

Topic 1

Topic 2

Results

Discussion

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Why Reconfigurable Architectures?

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Mark Papermaster: “Advancing EDA Through the Power of AI and High-performance Computing”, DAC59 Keynote, 2022

Hosted by a CPU

    • Design limited by the bus bandwidth!
      • carefully design memory & bus to avoid this bottleneck!

Yes, but ...

    • Optimized for a domain
      • Multiple kernels
      • Close to ASICs at the kernel level
    • Efficient execution of the kernels (latency and energy)

General purpose CPU

GPU

Domain specific

Applications

Performance / Watt

  • better than ASIC?

Intro

Topic 1

Topic 2

Results

Discussion

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Next steps: open-source design frameworks

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Maturity level (compile, explore, sim, validate)

C

SCALA-based

ADL*

Python, DSL, C/C++

Annotated C

C, OpenMP

Morpher ADL

CGRA-ME

Pillars

OpenCGRA

CCF

RIKEN

Morpher

+addons

(REVAMP)

*Architecture Description Language (ADL)

C

SCALA-based

ADL*

Python, DSL, C/C++

Annotated C

C, OpenMP

Morpher ADL

Intro

Topic 1

Topic 2

Results

Discussion

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Your Name � �EPFL - Embedded Systems Laboratory�your.email@epfl.ch

Thank you!

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