A R M Processor

21CSE45A

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MODULE 5

ARM Processor

Memory hierarchy

Mr.Bhaskar S.V

ARM Processor

Memory hierarchy- Processor Registers:

Mr.Bhaskar S.V

• The fastest access to data are held in processor registers.

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• Therefore, if we consider the registers to be part of the memory hierarchy, then the processor registers are at the top in terms of speed of access.

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• Registers provide only a tiny portion of the required memory

ARM Processor

Memory hierarchy- Processor Cache

Mr.Bhaskar S.V

• Relatively small amount of memory that can be implemented directly on the processor chip. This memory, called a processor cache

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• It holds copies of the instructions and data stored in a much larger memory that is provided externally

ARM Processor

Memory hierarchy- Processor Cache

Mr.Bhaskar S.V

• A primary cache (L1)
• This cache is small and its access time is similar to that of processor registers.
• is always located on the processor chip

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• Secondary cache(L2)
• A larger, and hence slightly slower,
• is always located on the processor chip

ARM Processor

Memory hierarchy- Main memory

Mr.Bhaskar S.V

• This is a large memory implemented using dynamic memory components.

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• The main memory is much larger but significantly slower than cache memories.

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ARM Processor

Memory hierarchy- Secondary Memory

Mr.Bhaskar S.V

• very large amount of inexpensive memory, and they are widely used as secondary storage in computer systems.

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• They are very slow compared to the main memory. They represent the bottom level in the memory hierarchy.

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ARM Processor

Cache Memory

Mr.Bhaskar S.V

• The cache is a small and very fast memory, interposed between the processor and the main memory.

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ARM Processor

Cache Memory-locality of reference

Mr.Bhaskar S.V

• phenomenon in which a computer program tends to access same set of memory locations for a particular time period.
• locality of reference increase the speed
• Many instructions in localized areas of the program are executed repeatedly during some time period.
• This behavior shows itself in two ways: temporal and spatial.

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ARM Processor

Cache Memory-spatial.

Mr.Bhaskar S.V

ARM Processor

Cache Memory-temporal

Mr.Bhaskar S.V

• temporal

ARM Processor

Mapping Functions

Mr.Bhaskar S.V

ARM Processor

Mr.Bhaskar S.V

ARM Processor

Mr.Bhaskar S.V

ARM Processor

Mapping Functions -Direct Mapping

Mr.Bhaskar S.V

• a certain block of the main memory would be able to map a cache only up to a certain line of the cache.
• Cache line number = (Address of the Main Memory Block ) Modulo (Total number of lines in Cache)

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ARM Processor

Mapping Functions -Direct Mapping

Mr.Bhaskar S.V

• Example:
• Let us consider that particular cache memory is divided into a total of ‘n’ number of lines.
• Then, the block ‘j’ of the main memory would be able to map to line number only of the cache (j mod n).

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ARM Processor

Mapping Functions -Direct Mapping

Mr.Bhaskar S.V

• In the case of direct mapping,
• There is no requirement for a replacement algorithm.
• It is because the block of the main memory would be able to map to a certain line of the cache only.
• Thus, the incoming (new) block always happens to replace the block that already exists, if any, in this certain line.

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ARM Processor

Mapping Functions -Division of Physical Address

Mr.Bhaskar S.V

ARM Processor

Mapping Functions -Fully Associative Mapping

Mr.Bhaskar S.V

• main memory block is capable of mapping to any given line of the cache that’s available freely at that particular moment.
• It helps us make a fully associative mapping comparatively more flexible than direct mapping.

ARM Processor

Mapping Functions -Fully Associative Mapping

Mr.Bhaskar S.V

• Every single line of cache is available freely.
• Thus, any main memory block can map to a line of the cache.
• In case all the cache lines are occupied, one of the blocks that exists already needs to be replaced..

ARM Processor

Mapping Functions -Fully Associative Mapping

Mr.Bhaskar S.V

• The Need for Replacement Algorithm.
• The replacement algorithm suggests a block that is to be replaced whenever all the cache lines happen to be occupied.
• So, replacement algorithms such as LRU Algorithm, FIFO Algorithm, etc., are employed.

ARM Processor

Mapping Functions -K-way Set Associative Mapping

Mr.Bhaskar S.V

• The grouping of the cache lines occurs into various sets where all the sets consist of k number of lines.

ARM Processor

Mapping Functions -K-way Set Associative Mapping

Mr.Bhaskar S.V

• Any given main memory block can map only to a particular cache set.
• However, within that very set, the block of memory can map any cache line that is freely available.
• The cache set to which a certain main memory block can map is basically given as follows:

ARM Processor

Mapping Functions -K-way Set Associative Mapping

Mr.Bhaskar S.V

• Cache set number = ( Block Address of the Main Memory ) Modulo (Total Number of sets present in the Cache)

ARM Processor

Mapping Functions -K-way Set Associative Mapping

Mr.Bhaskar S.V

• Cache set number = ( Block Address of the Main Memory ) Modulo (Total Number of sets present in the Cache)

ARM Processor

Mr.Bhaskar S.V

ARM Processor

Mapping Functions

Mr.Bhaskar S.V

• Three mapping techniques are:

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• Direct Mapping
• Associative Mapping
• Set-Associative mapping

ARM Processor

cache’s replacement algorithm.

Mr.Bhaskar S.V

• When the cache is full and a memory word (instruction or data) that is not in the cache is referenced, the cache control hardware must decide which block should be removed to create space for the new block that contains the referenced word.
• The collection of rules for making this decision constitutes the cache’s replacement algorithm.

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ARM Processor