VLSI Design – 18EC72

Course Objective

• Impart knowledge of MOS transistor theory and CMOS technologies
• Learn the operation principles and analysis of inverter circuits.
• Design Combinational, Sequential and dynamic logic circuits as per the requirements.
• Infer the operation of Semiconductors Memory circuits.
• Demonstrate the concepts of CMOS testing.

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Syllabus

• M1: Introduction & MOS Transistor Theory.
• M2: Fabrication & Scaling of MOS Circuits.
• M3: Delay & Combinational Circuit Design.
• M4: Sequential Circuit Design & Dynamic logic circuits.
• M5: Semiconductor Memories ,Testing & Verification.

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Text Book

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Text 1

Text 2

Course Outcomes

• Demonstrate understanding of MOS transistor theory, CMOS fabrication flow and technology scaling.
• Draw the basic gates using the stick and layout diagrams with the knowledge of physical design aspects.
• Demonstrate ability to design Combinational, sequential and dynamic logic circuits as per the requirements .
• Interpret Memory elements along with timing considerations.
• Interpret testing and testability issues in VLSI Design .

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Module 1

Introduction: A Brief History, MOS Transistors, CMOS Logic MOS Transistor Theory, Ideal I-V Characteristics, Non-ideal I-V Effects, DC Transfer Characteristics

(1.1 to 1.4, 2.1, 2.2, 2.4, 2.5 of TEXT2).

Introduction

(1.1 to 1.4, 2.1, 2.2, 2.4, 2.5 of Text 2)

Discrete Transistors and Circuits

• The transistor succeeded the valve in the late 1940s
• Electronic engineers began to design complex circuits using discrete components – transistors, resistors, capacitors
• Performance and other problems were noticed due to the number of separate components
• Circuits were unreliable and heavy
• High power consumption – long time to assemble
• Expensive to produce

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The Solution – Integrated Circuits

• Build entire circuit on a wafer of silicon
• Use masking and spraying techniques in manufacture
• Pure silicon wafers made from large crystals of silicon
• Areas of silicon doped with suitable elements e.g. Boron
• Conductive tracks made from aluminium
• Use this technique to produce other components e.g. capacitors and resistors on the same wafer

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Problems solved

• Inter-device distances reduced – faster circuits
• Lightweight circuits – suitable for space travel
• Cheaper assembly cost – after recovery of R&D costs
• Identical circuit properties – better matching
• Less power required – less heat dissipated
• Smaller circuits – smaller devices could be built

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A Brief History

• In 1958, Jack Kilby built first Integrated Circuit flip-flop with two transistors at Texas Instruments
• No other technology in history has sustained such a high growth rate for so long
• Driven by miniaturization of transistor and improvement in manufacturing process
• Smaller ; Cheaper, faster, dissipate low power

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Invention of Transistor

• In 20^th Century, Large, Expensive, Power hungry and Unreliable Vacuum tubes ruled the world
• 1947: John Bardeen and Walter Brattain built First functioning point contact transistor at Bell Laboratories

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Integrated Circuit

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Moore's Law

• Defined by Dr. Gordon Moore during the sixties.
• Predicts an exponential increase in component density over time, with a doubling time of 18 months.
• Applicable to microprocessors, DRAMs , DSPs and other microelectronics.
• Monotonic increase in density observed since the 1960s.

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Annual Sales

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• >10¹⁹ transistors manufactured in 2008
• 1 billion for every human on the planet

Size of worldwide semiconductor market (Courtesy https://www.fortunebusinessinsights.com/toc/semiconductor-market-102365.)

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Size of worldwide semiconductor market (Courtesy https://www.fortunebusinessinsights.com/toc/semiconductor-market-102365.)

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IC Technologies

• Small Scale Integration (SSI) combined around 10 discrete components onto 5mm square of silicon substrate.
• SSI led to Medium Scale Integration (MSI), then Large Scale Integration (LSI) with many thousands of components in the same area of silicon.
• Very Large Scale Integration (VLSI) provided the means to implement around 1 million components per chip.
• Current technology produces silicon wafers with around 50 million components per chip. The Pentium 4 had around 55 million components on the wafer (2003).

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IC Technologies

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Corollary of Moore’s Law

• Many other factors grow exponentially, i.e. Clock Frequency, Processor Performance

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MOS Transistor

• Modulated by voltage applied to the gate (voltage controlled device)

• nMOS transistor: majority carriers are electrons (greater mobility), p-substrate doped (positively doped)

• pMOS transistor: majority carriers are holes (less mobility), n-substrate (negatively doped)

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nMOS Transistor

• Four terminals: gate, source, drain, body
• Gate–oxide–body stack looks like a capacitor
• Gate and body are conductors
• SiO₂ (oxide) is a very good insulator
• metal – oxide – semiconductor (MOS) capacitor

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pMOS Transistor

• Similar, but doping and voltages reversed
• Body tied to high voltage (V_DD)
• Gate low: transistor ON
• Gate high: transistor OFF
• Bubble indicates inverted behavior

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MOS Transistor as a switch

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MOS Transistors Symbols

D

S

G

D

S

G

G

S

D

D

S

G

NMOS

Enhancement

NMOS

PMOS

Depletion

Enhancement

B

NMOS with

Bulk Contact

Channel

MOS Transistor Theory

• The MOS transistor is a majority-carrier device in which the current in a conducting channel between source and drain is controlled by a voltage applied to the gate
• MOS Structure

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Accumulation

Depletion

Inversion

MOS Terminal Voltages

• Mode of operation depends on V_g, V_d, V_s
• V_gs = V_g – V_s
• V_gd = V_g – V_d
• V_ds = V_d – V_s = V_gs - V_gd
• Source and drain are symmetric diffusion terminals
• By convention, source is terminal at lower voltage nMOS body is generally grounded
• Three regions of operation
• Cutoff
• Linear
• Saturation

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MOS Transistors

• Silicon (Si), a semiconductor, forms the basic starting material for most integrated circuits
• Three-dimensional lattice of atoms
• It forms covalent bonds with four adjacent atoms
• The conductivity can be raised by introducing small amounts of impurities – dopants
• A dopant from Group V - such as arsenic, has five valence electrons
• It replaces a silicon atom in the lattice and still bonds to four neighbors
• This an n-type semiconductor because the free carriers are negatively charged electrons
• Group III dopant, such as boron, has three valence electrons
• Missing electron, or hole, can propagate about the lattice
• The hole acts as a positive carrier so we call this a p-type semiconductor

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MOS Transistors

• A junction between p-type and n-type silicon is called ??
• forward bias condition
• reverse bias condition
• A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing several layers of conducting and insulating materials to form a sandwich-like structure
• Manufactured using a series of chemical processing steps involving oxidation of the silicon, selective introduction of dopants, and deposition and etching of metal wires and contacts
• Transistors are built on nearly flawless single crystals of silicon - thin flat circular wafers of 15–30 cm in diameter
• Transistor operation is controlled by electric fields - Metal Oxide Semiconductor Field Effect Transistors

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MOS Transistors

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• Stack of the conducting gate
• Silicon dioxide
• silicon wafer - substrate, body
• Gate has been formed from polycrystalline silicon (polysilicon)
• Body is typically grounded

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MOS Transistors

• The gate is a control input
• pMOS transistor behavior is the

opposite of the nMOS

• +ve voltage is usually called VDD
• 1970s and 1980s, VDD was set to 5v
• Recent transistors supplies of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V
• The low voltage is called GROUND (GND) or VSS and represents a logic 0

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MOS Transistors

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MOS Transistors Theory

• MOS transistor is a majority-carrier device
• nMOS transistor, the majority carriers are electrons
• pMOS transistor, the majority carriers are holes
• Behavior of MOS transistors

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MOS Transistors Theory

• MOS transistor is a majority-carrier device
• nMOS transistor, the majority carriers are electrons
• pMOS transistor, the majority carriers are holes
• Behavior of MOS transistors

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MOS Transistors Theory

• MOS transistor is a majority-carrier device
• nMOS transistor, the majority carriers are electrons
• pMOS transistor, the majority carriers are holes
• Behavior of MOS transistors

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MOS Transistors – cut off region

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MOS Transistors – linear region

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MOS Transistors – saturation region

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MOS Transistors

• Conduction characteristics of an MOS transistor can be categorized as
• Cut off - current flow is due to source – drain leakage current
• Linear region – weak inversion, drain current increases linearly with gate voltage
• Saturation region – channel is strongly inverted and drain current is independent of drain voltage
• An abnormal conduction condition called ‘avalanche break down or punch through’ – high voltage applied to the drain; gate has no control over drain current.

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pMOS Transistors

• n-type body is tied to a high potential
• When the gate is also at a high –

no current flows

• When Vg is lowered by a threshold Vt - holes are attracted to form a p-type channel
• The threshold voltages of the two types of transistors are not necessarily equal - Vtn and Vtp
• CMOS gates - source is the terminal closer to the supply rail
• CMOS gates - drain is the terminal closer to the output
• The gate of an MOS transistor is inherently a good capacitor
• Parasitic capacitance

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Ideal I-V Characteristics (first order model)

• Idealized I-V model provides a general qualitative understanding of transistor
• MOS transistors have three regions of operation
• Cutoff or subthreshold region
• Linear region
• Saturation region
• Channel length is long enough
• This model is variously known as the

long-channel, ideal, first-order, or Shockley model

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Ideal I-V Characteristics

2. Linear region

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Ideal I-V Characteristics

1. Saturation region

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Ideal I-V Characteristics

• nMOS

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Ideal I-V Characteristics

• pMOS

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Non - Ideal I-V Characteristics

• The long-channel I-V model neglects many effects
• Mobility degradation and Velocity saturation
• Channel length modulation
• Body effect
• Drain-induced barrier lowering
• Short channel effect
• Sub threshold conduction
• Electrons tunnel through the gate, causing some gate leakage current
• Mobility and threshold voltage decrease with rising temperature

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Non - Ideal I-V Characteristics

• The long-channel I-V model neglects many effects
• The saturation current increases less than quadratically with increasing Vgs
• Caused by two effects: velocity saturation and mobility degradation
• At high vertical field strengths (Vgs /tox ) - the carriers scatter off the oxide interface more often
• This mobility degradation effect also leads to less current than expected at high Vgs
• At high lateral field strengths - carrier velocity ceases to increase linearly with field strength
• This is called velocity saturation and results in lower Ids than expected at high Vds
• saturation current of the non ideal transistor increases somewhat with Vds – caused by channel length modulation
• Higher Vds increases the size of the depletion region around the drain

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Non - Ideal I-V Characteristics

• The threshold voltage indicates the gate voltage necessary to invert the channel
• Vt is primarily determined by the oxide thickness and channel doping levels
• Fields in the transistor have some effect on the channel, effectively modifying the threshold voltage
• Increasing the potential between the source and body raises the threshold through the body effect
• Increasing the drain voltage lowers the threshold through drain-induced barrier lowering
• Increasing the channel length raises the threshold through the short channel effect

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Non - Ideal I-V Characteristics

• Subthreshold conduction - the current drops off exponentially rather than abruptly becoming zero
• The gate Ig is ideally 0
• Electrons tunnel through the gate, causing some gate leakage current
• The source and drain diffusions are typically reverse-biased diodes and also experience junction leakage into the substrate
• Both mobility and threshold voltage decrease with rising temperature
• Lower Ids at high temperature
• Higher leakage current at high temperature

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Velocity saturation and mobility degradation

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• Carrier drift velocity, and hence current, is proportional to the lateral electric field Elat = Vds /L between source and drain
• Long channel model assumed that carrier mobility is independent of the applied fields – doesn't hold good for strong lateral or vertical fields
• At sufficiently high lateral fields, the current saturates at some value dependent on the maximum carrier velocity - velocity saturation
• High voltage at the gate of the transistor attracts the carriers to the edge of the channel, causing collisions with the oxide interface that slow the carriers - mobility degradation

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Channel Length Modulation

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• Current drawn through the channel is nearly a constant independent of drain voltage in saturation mode
• Ids is independent of Vds for a transistor in saturation - current source
• The depletion region effectively shortens the channel length to Leff = L – Ld
• Shorter channel length results in higher current
• Channel length modulation reduces the gain of amplifiers

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Channel Length Modulation

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Body Effect

• We have considered a transistor to be a three-terminal device with gate, source, and drain
• Body is an implicit fourth terminal
• When a voltage Vsb is applied between the source and body - increases the amount of charge required to invert the channel
• Hence it increases the threshold voltage

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Drain-Induced Barrier Lowering

• The drain voltage Vds creates an electric field that affects the threshold voltage
• This drain-induced barrier lowering (DIBL) effect is especially pronounced in short-channel transistors
• Drain-induced barrier lowering causes Ids to increase with Vds in saturation

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Sub threshold Conduction

• The long-channel transistor I-V model assumes current only flows from source to drain when Vgs > Vt
• Current does not abruptly cut off below threshold, but rather drops off exponentially – known as leakage
• When the gate voltage is high, the transistor is strongly ON
• When the gate falls below Vt , the exponential decline in current appears as a straight line on the logarithmic scale
• This regime of Vgs < Vt is called weak inversion
• Subthreshold conduction is used to advantage in very low-power circuits
• Subthreshold leakage increases exponentially as Vt decreases or as temperature rises

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Sub threshold Conduction

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Junction Leakage

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• The p-n junction between diffusion and the substrate or well form diodes
• The substrate and well are tied to GND or VDD to ensure these diodes do not become forward biased in normal operation
• When a junction is reverse biased by significantly more than the thermal voltage - leakage is just –Is

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Tunneling/ Gate Leakage

• As the gate-oxide is scaled down, breakdown of the oxide and oxide reliability becomes more of a concern
• For gate oxides thinner than 1.5–2.0 nm there is a nonzero probability that an electron in the gate will find itself on the wrong side of the oxide
• This effect of carriers crossing a thin barrier is called tunneling
• Results in gate leakage current
• The probability of tunneling drops off exponentially with oxide thickness

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Tunneling/ Gate Leakage

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Temperature Dependence

• Transistor characteristics are influenced by temperature - Carrier mobility decreases with temperature
• vsat also decreases with temperature, dropping by about 20% from 300 to 400 K
• The magnitude of the threshold voltage decreases nearly linearly with temperature
• Ion at high VDD decreases with temperature. Subthreshold leakage increases exponentially with temperature

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Temperature Dependence

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Non - Ideal I-V Characteristics

• The long-channel I-V model neglects many effects

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Static CMOS Inverter DC Characteristics

• A complementary CMOS inverter is realised by the series connection of a P and N devices

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Static CMOS Inverter DC Characteristics

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Beta Ratio Effects

• If the beta ratio is changes – switching threshold moves
• Usually skewed by adjusting the widths of transistor while maintaining minimum length for speed

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Noise Margin

• Noise margin is closely related to the DC voltage characteristics
• This parameter allows you to determine the allowable noise voltage on the input of a gate so that the output will not be corrupted
• The specification most commonly used to describe noise margin (or noise immunity) uses two parameters
• LOW noise margin, NML
• HIGH noise margin, NMH
• NML is defined as the difference in maximum LOW input voltage recognized by the receiving gate and the maximum LOW output voltage produced by the driving gate
• The value of NMH is the difference between the minimum HIGH output voltage of the driving gate and the minimum HIGH input voltage recognized by the receiving gate

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Noise Margin

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Noise Margin

• Output is degraded when the input is at its worst legal value – noise feed through / propagated noise
• CMOS Inverter Noise Margins

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Text Books

• 1. “CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo Kang & Yosuf Leblebici, Third Edition, Tata McGraw-Hill.
• 2. “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E. Weste, and David Money Harris4th Edition, Pearson Education.

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• Note : Images and figures have been taken from prescribed textbooks.

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Reference Books

• 1. Adel Sedra and K. C. Smith, “Microelectronics Circuits Theory and Applications”, 6th or 7th Edition, Oxford University Press, International Version, 2009.
• 2. Douglas A Pucknell & Kamran Eshragian, “Basic VLSI Design”, PHI 3rd Edition, (original Edition – 1994).
• 3. Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, TMH, 2007.

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