Discussion 6: RISC-V Single Cycle Datapath

March 7, 2019

Attendance:

tinyurl.com/logisimiscool

Wordbank for rounded squares:

ALU (Arithmetic Logical Unit), Branch Comparator, Data Memory, Immediate Generator, Instruction Memory, PC (Program Counter), Register File

Program Counter:

A register that stores what line the CPU is at the program. Does not store the line itself; just the address.

Instruction Memory:

The program counter passes the address to this, so that the CPU can fetch the actual line in the program that it needs.

Register File:

Based on the instruction memory, this component will then get the corresponding register values.

Immediate Generator:

If we need an immediate, then we will grab it in this stage. Notice how it’s parallel to the register file- we grab immediates the same time we grab register values.

Branch Comparator:

If the instruction is a branch instruction, this is where we decide if we are going to branch or not.

Arithmetic Logical Unit:

This is where we compute operations (addition, multiplication, xor, et. al.) on two values to produce another value. Basically the calculator of the CPU.

Data Memory:

If we need to retrieve something from memory (or put something in memory), this is where we do it. Typically the slowest part of the entire CPU.

Word bank for square-y squares:

PCSel (Program Counter Select)

RegWEn (Register Write Enabled)

ImmSel (Immediate Select)

BrEq (Branch if Equal)

BrUn (Branch is Unsigned)

BrLt (Brach if Less Than)

ASel (A Select)

BSel (B Select)

ALUSel (ALU Select)

MemRW (Memory Read Write)

WBSel (Write Back Select)

Register Write Enabled:

Do we allow writing to the register file? We have this so that we don’t accidentally overwrite anything.

Immediate Select:

What type of immediate do we use (if we do use one)?

Branch is Unsigned (or just Branch Unsigned):

Tells us if the values we are comparing are unsigned or not. (Only really used in bltu/bgeu)

Branch (if) Equal / Branch (if) Less Than

Passed by the branch comparator to the control logic (not vice versa) telling us if the instruction we’ve read is blt/bltu or beq! Will be used wayyy later...

PCSel (PC Select):

...here. If either BrEq/BrLt return a 1, that means that we have to use the (not yet calculated) new address location instead of the standard PC + 4 (next address). Note jump sets this to 1 automatically.

3 Different Possible Input Combinations into the ALU:

“A” Multiplexer

“B” Multiplexer

Example Usage

Register Value (rs1)

Register Value (rs2)

add a0, t1, t0

Register Value (rs1)

Immediate Value (imm)

addi a0, t1, 5

Program Counter (PC)

Immediate Value (imm)

jal ra, label_five_lines_above

“A” Multiplexer

“B” Multiplexer

ASel (A Select), BSel (B Select):

Selects which inputs we want to send into the Arithmetic Logical Unit (ALU). Controls the two muxes shown here.

ALU Sel (ALU Select):

Selects the right operation to output in the ALU.

Memory Read/Write:

Selects if we want to read from the memory or write from the memory (or do neither).

Writeback Select:

Selects whether or not we want to write any data back to the registers.

Five Datapath Stages:

Instruction Fetch, Instruction Decode, Execute, Memory, Write Back

Instruction Fetch:

Sends address to instruction memory, reads instruction memory at that address

Instruction Decode:

Parses the instructions, creates the immediates, reads registers from the regfile. Basically sets everything up from the instruction.

Execute:

Performs ALU operations and does the branch comparisons. Basically takes the values that were set up, and executes it.

Memory:

Reads/writes data from memory

Write Back:

Writes back PC + 4 (next address) or the ALU result to PC. Also writes data back to the registers if needed.

Discussion 6 - Google Slides