Wakey-Wakey
A Low-Power Reconfigurable Wake Word Accelerator�{eldrick, mjpauly}@stanford.edu
Overview
Wake Word Recognition
Wake words are certain words or phrases that activate a system
“Hey Siri”, “Ok Google”, “Alexa”�
Can be a standalone interface or paired with automatic speech recognition systems��Enables:
“Cooper, go fetch!”
Motivation
Human speech interfaces enable...
But face challenges in...
System Goals
Months-Long Longevity
01
02
03
Conversational Robustness
Accuracy & Reconfigurability
We’re building a wake-word recognition system targeting:
System Architecture
Signal Processing Pipeline
Digital Front End
Conditions incoming digital audio signal with FIR filter.�Contains gating controller
Acoustic Featurization
Transforms conditioned audio signal into Mel-Frequency Cepstral Coefficients (MFCC), a type of acoustic feature
Word Recognition
Accelerates a 1D CNN network for recognizing the chosen wake word
DFE
ACO
WRD
External I/O
2) I2C / SPI / PDM to ADC + Microphone
Digitized Audio�(VM3011:“Zero-Power Listening” Microphone + ADC)
Software Backend�Edge Impulse
check it out at https://www.edgeimpulse.com/
Neural Network Architecture
Estimate for Cortex-M4F @ 80MHz
1347 Parameters
Potential Extensions
Additional NN arch or MFCC parameter configurability
Audio passthrough after wake word detection
01
02
TBD! Drop us a suggestion :)
03
Timeline
Spring Break - Software Modeling (Gold Model), Existing IP Search
Spring Week 1 - WRD RTL + TB, ACO RTL + TB, Initial flow up to Simulation and Compilation
Spring Week 2 - WRD RTL + TB, ACO RTL + TB, Initial flow up to Synthesis, Order ADC/MIC
Spring Week 3 - WRD RTL + TB, ACO Verified, DFE RTL + TB, ADC/MIC Physical Testing
Spring Week 4 - WRD Verified, CFG RTL + TB, DFE Verified, ADC/MIC Verified
Spring Week 5 - CFG Verified, Initial Full System Synthesis, initial flow up to floorplan
Spring Week 6 - Full system verified, full system synthesis, initial flow up to signoff
Spring Week 7 - Floorplanning, power design, clocking and STA, physical design iteration
Spring Week 8 - Physical design iteration, RTL improvements
Spring Week 9 - Pre-sign off checks and improvements
Spring Week 10 - Sign-off, Send to Foundry, Tapeout!
Questions?
{eldrick, mjpauly}@stanford.edu
Motivation
- One slide recap of the motivation for your project, application areas
Your Design
- This is your complete verilog/schematic design
- Show top level block diagram and component level diagrams
- Explain how each component works
Functional Verification
- Describe how you created your gold model
- Show a list of tests you ran and a plot/screenshot showing that each test passed. This includes component level basic unit tests, end to end application tests, tests considering noise, PVT corners, variation etc.
- What further tests will you run in the remaining weeks, such as post layout validation, integration testing with caravel, more applications etc.
Design Space Exploration
Show any experiments you did to make design choices, such as sweeps of component values, parameters etc.
Evaluation
Evaluation metrics include estimates of
- area (must fit in caravel user project area)
- max frequency (with no timing violations), throughput, latency
- power, energy
- circuit specific figures of merit (efficiency, accuracy/error, temperature/voltage sensitivity etc)
For digital designs, post synthesis numbers are okay.
Plan
Plan for the remaining 5 weeks.
We will be happy to review your presentations during office hours!
Wakey-Wakey
A Low-Power Reconfigurable Wake Word Accelerator�{eldrick, mjpauly}@stanford.edu
Design Review 2021-05-03
Motivation
Human speech interfaces enable...
But face challenges in...
Wake Word Recognition
Wake words are certain words or phrases that activate a system
“Hey Siri”, “Ok Google”, “Alexa”�
Can be a standalone interface or paired with automatic speech recognition systems��Enables:
“Cooper, go fetch!”
System Goals
Months-Long Longevity
01
02
03
Conversational Robustness
Accuracy & Reconfigurability
We’re building a wake-word recognition system targeting:
System Goals - Targets
Metric | Target | Achieved | Notes |
Area | < 10 mm2 | | MPW-TWO User Project Area Constraint |
Latency | < 250 ms | | Word Utterance to Wake Pin Assert |
Freq. | 4 MHz | | Determined by sampling rate needed for PDM |
Inference Energy Efficiency | ? pj/Op | | |
Idle Power Consumption | 0.89 mW | | 6 Months on Alkaline AA Battery (3.9 Watt Hrs) |
Test Set Accuracy | > 90% | | Google Speech Commands Dataset + Microsoft Scalable Noisy Speech Dataset �(Yes vs No/Unknown/Noise - 25 mins. per class) |
Model Size | | | Target set by Area & Test Set Accuracy |
Dev Notes
how did you model this in software?
code / plots figures here
clever tricks for approximating or modeling behavior
talk about any code or test infrastructure here
cocotb block diagram
System Architecture
Design Progress
RTL Complete and Verified
RTL Work In Progress
Software Gold Models Complete
DFE: The Digital Front-End!
DFE Architecture
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
Pulse Density Modulation (PDM) Signal
Microphone output: 1b data @ 4MHz
DFE output: 8b data @ 16kHz
Vesper VM3011
DFE Model
Software model
Processing Quality
how did you model this in software?
code / plots figures here
clever tricks for approximating or modeling behavior
talk about any code or test infrastructure here
Original Audio Sample
PDM modeled + filtered
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
Microphone output: 1b data @ 4MHz
DFE output: 8b data @ 16kHz
Vesper VM3011
DFE Architecture Detail
DFE Verification Plan
show passing test
show tests ran
talk about edge cases
talk about unit and integration testing
talk about future testing
DFE: The Digital Front-End!
ACO: The Acoustic Featurizer!
ACO Architecture
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
Mel Scale
ACO Model
how did you model this in software?
code / plots figures here
clever tricks for approximating or modeling behavior
talk about any code or test infrastructure here
ACO Architecture Detail
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
ACO Architecture Detail
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
ACO Architecture Detail
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
ACO Verification
show passing test
show tests ran
talk about edge cases
talk about unit and integration testing
talk about future testing
ACO: The Acoustic Featurizer!
WRD: The DNN Accelerator!
WRD Model
how did you model this in software?
code / plots figures here
clever tricks for approximating or modeling behavior
talk about any code or test infrastructure here
WRD Architecture
WRD Architecture
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
WRD Architecture
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
WRD Input
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
WRD Zero Pad
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
WRD 1D Convolution
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
∗
WRD 1D Convolution
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
∗
WRD 1D Convolution
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
∗
WRD 1D Convolution
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
∗
WRD 1D Convolution
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
∗
WRD 1D Convolution
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
∗
WRD 1D Convolution
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
∗
WRD 1D Convolution
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
WRD Convolution Layer HW
WRD Convolution Layer HW
WRD Convolution Layer HW
WRD Convolution Layer HW
WRD Convolution Layer HW
WRD Convolution Layer HW
WRD Convolution Layer HW
WRD Convolution Layer HW
WRD Convolution Layer HW
WRD Convolution Layer HW
WRD Convolution Layer HW
WRD Convolution Layer HW
Cycles through 8 filters to complete
WRD Convolution Layer HW
Cycles through 8 filters to complete
“Recycles” the input MFCCs 8 times
WRD Convolution Layer HW
Cycles through 8 filters to complete
“Recycles” the input MFCCs 8 times
8 Filters * 50 Frames = 400 total cycles
WRD 1D Convolution
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
WRD Max Pool
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
WRD Max Pool
detailed block diagram here
RTL level considerations
interesting wave diagrams here
describe constituent modules
describe input values
describe output values
Output of Conv -> Max Pool is serial data
Next conv layer expects 25 frames, each frame with 8 output channels - need to reshape data from serial to parallel
WRD Architecture
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
WRD Serial-In-Parallel-Out
WRD Architecture
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
WRD Conv 2
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
WRD Conv 2
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
WRD Fully Connected Layer
WRD Fully Connected Layer
Output of conv2 -> max_pool2 is 208 values, serial.
WRD Fully Connected Layer
2 classes = 2 weight banks
Class 1: Wake Word�Class 2: Not Wake Word
208 Weights Each
WRD Fully Connected Layer
208 Cycles to Complete
WRD Fully Connected Layer
Upon completion, compare 2 class values.
Class 1 > Class 2 = WAKE!
WRD Fully Connected Layer
Sustain WAKE for N cycles
WRD Detailed Architecture
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
WRD Detailed Architecture
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
WRD Architecture
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
WRD Verification
show passing test
show tests ran
talk about edge cases
talk about unit and integration testing
talk about future testing
WRD Verification
show passing test
show tests ran
talk about edge cases
talk about unit and integration testing
talk about future testing
WRD: The DNN Accelerator!
CFG: The DNN Configurator!
CFG Architecture
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
CFG Write Transaction
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
Write to Conv 1 Filter 0 Weight 0
CFG Read Transaction
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
Read Conv 1 Filter 0 Weight 0�
CFG Model
how did you model this in software?
code / plots figures here
clever tricks for approximating or modeling behavior
talk about any code or test infrastructure here
CFG: The DNN Configurator!
Let’s Zoom Back Out...
System Goals - Achieved
Metric | Target | Achieved | Notes |
Area | < 10 mm2 | WRD = 2 mm2, Total = 4 mm2 (est) | MPW-TWO User Project Area Constraint |
Latency | < 250 ms | ~ 152 us | Word Utterance to Wake Pin Assert, ~ 2447 Cycles |
Freq. | 4 MHz | 16 MHz | Determined by sampling rate needed for PDM |
Inference Energy Efficiency | ? pj/Op | | TODO: GL Sim via PrimeTime |
Idle Power Consumption | 0.89 mW | WRD = 0.794 mW | 6 Months on Alkaline AA Battery (3.9 Watt Hrs), OpenSTA Leakage Estimate |
Test Set Accuracy | > 90% | 96% | Google Speech Commands Dataset + Microsoft Scalable Noisy Speech Dataset �(Yes vs No/Unknown/Noise - 25 mins. per class) |
Model Size | | 1,140 Parameters (1,168 Bytes) | Target set by Area & Test Set Accuracy |
Microcontroller Comparison
Processing time on a Cortex-M4F @ 80MHz
MFCCs:
DNN:
Power comparison coming
System Goals - Post Route Power for WRD
15mW 4.8mW 0.79mW 20mW
Upcoming Development Schedule
talk about future RTL dev
talk about future test
talk about caravel integration
talk about physical design
talk about clock or power gating - ask what to go for here
talk about debug
talk about comparing to microcontroller
latency and power
WRD, post-route!
{eldrick, mjpauly}@stanford.edu
Questions?
Wakey-Wakey
A Low-Power Reconfigurable Wake Word Accelerator�{eldrick, mjpauly}@stanford.edu
Final Presentation 2021-05-25
High Level Overview
Recap: Where we were 3 weeks ago...
RTL Complete and Verified
RTL Work In Progress
Software Gold Models Complete
Now
Our Progress to Date
Architecture Progress To Date
Custom Model Training + Quantization
Architecture Progress To Date
Custom Training + Quantization Pipeline
So Many Block Diagrams!
Architecture Progress To Date
Custom Training + Quantization Pipeline
So Many Block Diagrams!
Microphone Part Selection + Acquisition
Implementation Progress to Date
39 custom verilog modules
Implementation Progress to Date
6,362 lines of custom RTL code
39 custom verilog modules
Verification Progress to Date
5,596 lines of test bench code
734 lines of software model code
All modules have passing unit tests
All subsystems have passing integration tests
Physical Design Progress to Date
Fully open source flow using openlane
Physical Design Results
Flow on DFE + CFG + WRD runs to completion
Meets Timing, Area�(16 MHz, 2.5 mm2)
Some Antenna Violations to Resolve
Physical Design Results
Flow on full user design runs to placement, CTS
Physical Design Results
Flow on full user design runs to placement, CTS
Meets Timing, Area�(16 MHz, 4.5 mm2)
hold slack - 0.19 ns
setup slack - 17.53 ns
critical path in ACO
working on getting a per-module area breakdown
Physical Design Results
Flow on full user design runs to placement, CTS
Meets Timing, Area�(16 MHz, 4.5 mm2)
Failed at 6 AM today at Global Route
Recap: System Goals
Metric | Target | Achieved | Notes |
Area | < 10 mm2 | WRD = 2 mm2, Total = 4 mm2 (est) | MPW-TWO User Project Area Constraint |
Latency | < 250 ms | ~ 152 us | Word Utterance to Wake Pin Assert, ~ 2447 Cycles |
Freq. | 4 MHz | 16 MHz | Determined by sampling rate needed for PDM |
Inference Energy Efficiency | ? pj/Op | | TODO: GL Sim via PrimeTime |
Idle Power Consumption | 0.89 mW | WRD = 0.794 mW | 6 Months on Alkaline AA Battery (3.9 Watt Hrs), OpenSTA Leakage Estimate |
Test Set Accuracy | > 90% | 96% | Google Speech Commands Dataset + Microsoft Scalable Noisy Speech Dataset �(Yes vs No/Unknown/Noise - 25 mins. per class) |
Model Size | | 1,140 Parameters (1,168 Bytes) | Target set by Area & Test Set Accuracy |
System Goals
Metric | Target | Achieved | Notes |
Area | < 10 mm2 | 4.5mm2 | MPW-TWO User Project Area Constraint |
Latency | < 250 ms | ~ 152 us | Word Utterance to Wake Pin Assert, ~ 2447 Cycles |
Freq. | 4 MHz | 16 MHz | Determined by sampling rate needed for PDM |
Inference Energy Efficiency | ? pj/Op | | TODO: GL Sim via PrimeTime |
Idle Power Consumption | 0.89 mW | | 6 Months on Alkaline AA Battery (3.9 Watt Hrs), OpenSTA Leakage Estimate |
Test Set Accuracy | > 90% | 96% | Google Speech Commands Dataset + Microsoft Scalable Noisy Speech Dataset �(Yes vs No/Unknown/Noise - 25 mins. per class) |
Model Size | | 1,140 Parameters (1,168 Bytes) | Target set by Area & Test Set Accuracy |
Recap: Development Schedule
talk about future RTL dev
talk about future test
talk about caravel integration
talk about physical design
talk about clock or power gating - ask what to go for here
talk about debug
talk about comparing to microcontroller
latency and power
Recap: Development Schedule
talk about future RTL dev
talk about future test
talk about caravel integration
talk about physical design
talk about clock or power gating - ask what to go for here
talk about debug
talk about comparing to microcontroller
latency and power
What’s Next
What’s Next
Test classification accuracy of RTL end-to-end
What’s Next
Test writing parameters via the management core and the wishbone interface
What’s Next
Design for test
What’s Next
Improve idle power consumption
What’s Next
Asynchronous assert, synchronous deassert resets
What’s Next
Capture microphone test samples
What’s Next
Estimate power and timing more accurately with PrimeTime
{eldrick, mjpauly}@stanford.edu
Questions?
1. Start with a brief recap of what your project was about, show the system block diagram of the chip you taped out, and how it works.
2. Describe your chip bringup process: what software you wrote, tests you ran and how you debugged the board and the chip. Include some pictures of the working board + chip showing signs of life.
3. Present your measured results, and compare them with the results from your pre-tapeout simulations. If you were not able to test your chip fully, describe the partial testing you were able to do, and what issues you are running into.
4. Finally, summarize the key contributions and takeaways of the project, including things you think you should have done differently pre-tapeout to make bringup easier.
Wakey-Wakey
A Low-Power Reconfigurable Wake Word Accelerator�{eldrick, mjpauly}@stanford.edu
Bring-Up Presentation 2022-06-01
Wake Word Recognition
Wake words are certain words or phrases that activate a system
“Hey Siri”, “Ok Google”, “Alexa”�
Can be a standalone interface or paired with automatic speech recognition systems��Enables:
“Cooper, go fetch!”
Motivation
Human speech interfaces enable...
But face challenges in...
System Goals
Months-Long Longevity
01
02
03
Conversational Robustness
Accuracy & Reconfigurability
We’re building a wake-word recognition system targeting:
Hardware <> Software Co-Design
HW Conscious Quantization and Network Design
Fully Custom Verilog Modules
Low Power Microphone HW
High Level Overview
The Bring Up Process - Challenges
Only 1 Copy of Testboard
Received Test Board on Feb 1
Distributed / Remote Bring Up
Reliable GPIO Config
The Bring Up Process
Feb 1 - Received chips and test board
The Bring Up Process
Feb 28 - Successfully flashed caravel firmware!
And successfully tested wishbone parameter writes to internal DFFRAM!!!
https://github.com/eldrickm/caravel_board/blob/main/firmware/wakey/wakey.c
May 31 - Fully tested and verified all memory locations in the DFFRAM!!!!!
The Bring Up Process
It’s Alive!
CFG Architecture
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
CFG Write Transaction
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
Write to Conv 1 Filter 0 Weight 0
CFG Read Transaction
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
Read Conv 1 Filter 0 Weight 0�
CFG Model
how did you model this in software?
code / plots figures here
clever tricks for approximating or modeling behavior
talk about any code or test infrastructure here
It’s Alive!
The Bring Up Process
Vesper Microphone voice activity detection
Current Challenge: MPRJ GPIO Config
DFE Architecture
design considerations�
parameter space exploration
experiments conducted
interesting technical hurdles
put component level block diagram here
Pulse Density Modulation (PDM) Signal
Microphone output: 1b data @ 4MHz
DFE output: 8b data @ 16kHz
Vesper VM3011
Current Challenge: GPIO Config
Current Challenge: GPIO Config
System Goals - ALL TBD!
Metric | Target | Achieved | Observed In Practice: | Notes |
Area | < 10 mm2 | 4.5mm2 | N/A | MPW-TWO User Project Area Constraint |
Latency | < 250 ms | ~ 152 us | TBD | Word Utterance to Wake Pin Assert, ~ 2447 Cycles |
Freq. | 4 MHz | 16 MHz | TBD | Determined by sampling rate needed for PDM |
Inference Energy Efficiency | ? pj/Op | | TBD | |
Idle Power Consumption | 0.89 mW | | TBD | 6 Months on Alkaline AA Battery (3.9 Watt Hrs), OpenSTA Leakage Estimate |
Test Set Accuracy | > 90% | 96% | TBD | Google Speech Commands Dataset + Microsoft Scalable Noisy Speech Dataset �(Yes vs No/Unknown/Noise - 25 mins. per class) |
Model Size | | 1,140 Parameters (1,168 Bytes) | N/A | Target set by Area & Test Set Accuracy |
Key Contributions and Takeaways
Codesign
Hardware
Software
1 Year Rewind: What to Do Differently
Glamour Shots
Glamour Shots
Matthew’s housewarming gift for Eldrick :)
eldrick@alumni.stanford.edu
mjpauly@stanford.edu
Questions?
Wakey-Wakey
These exciting new inventions present endless possibilities
of how technology can shape the future for the better.
Health
& Wellness
CUSTOM ANTIBIOTICS
& VACCINES
Presentations are tools that can be used as reports, and more. It is mostly presented before an audience. It serves
a variety of purposes, making presentations powerful tools for convincing and teaching.
Presentations are tools that can be used as reports, and more. It is mostly presented before an audience. It serves
a variety of purposes, making presentations powerful tools for convincing and teaching.
Presentations are tools that can be used as reports, and more. It is mostly presented before an audience. It serves
a variety of purposes, making presentations powerful tools for convincing and teaching.
01
02
03
SMART CLOTHING
& FIXTURES
Presentations are communication tools that can be used as demonstrations, lectures, speeches, reports, and more. It is mostly presented before an audience. It serves a variety of purposes, making presentations powerful tools for convincing and teaching.
Presentations are communication tools that can be used as demonstrations, lectures, speeches, reports, and more. It is mostly presented before an audience. It serves a variety of purposes, making presentations powerful tools for convincing and teaching.
Computer Science and Manufacturing
ADVANCED
ARTIFICIAL INTELLIGENCE
Presentations are communication tools that can be used as demonstrations, lectures, speeches, reports, and more. It is mostly presented before an audience. It serves a variety of purposes, making presentations powerful tools for convincing and teaching.
Presentations are communication tools that can be used as demonstrations, lectures, speeches, reports, and more. It is mostly presented before an audience. It serves a variety of purposes, making presentations powerful tools for convincing and teaching.
ADVANCED
3D PRINTING
Presentations are communication tools that can be used as demonstrations, lectures, speeches, reports, and more. It is mostly presented before an audience.
01
Presentations are communication tools that can be used as demonstrations, lectures, speeches, reports, and more. It is mostly presented before an audience.
Presentations are communication tools that can be used as demonstrations, lectures, speeches, reports, and more. It is mostly presented before an audience.
02
03
Energy and Agriculture
FLOATING OR
HIGH RISE FARMS
Presentations are communication tools that can be used as demonstrations, lectures, speeches, reports, and more. It is mostly presented before an audience. It serves a variety of purposes, making presentations powerful tools for convincing and teaching.
SOLAR POWER INNOVATIONS
Presentations are communication tools that can be used as demonstrations, lectures, speeches, reports, and more. It is mostly presented before an audience. It serves a variety of purposes, making presentations powerful tools for convincing and teaching.
Transportation
& Space Research
HYPERSPEED TRANSPORTATION
Presentations are communication tools that can be used as demonstrations, lectures, speeches, reports, and more. It is mostly presented before an audience. It serves a variety of purposes, making presentations powerful tools for convincing and teaching.
SPACE TOURISM
& COLONIZATION
Presentations are communication tools that can be used as demonstrations, lectures, speeches, reports, and more. It is mostly presented before an audience. It serves a variety of purposes, making presentations powerful tools for convincing and teaching.