• Multivibrators
• Bistable: R-S latch
• Monostable: one-shots
• Astable: 555 Timer (today's lab)

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The R-S latch

• Cross-coupled gates form an R-S latch with two stable states (bistable multivibrator)

S=1, R=0 : Q=1, Q'=0

S=0, R=1 : Q=0, Q'=1

S=0, R=0 : hold state

S=1, R=1 : unstable

http://fac-web.spsu.edu/cs/faculty/bbrown/web_lectures/sequential/

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One-shot

• A monostable multivibrator can be very useful
• produces an output pulse with the correct voltage levels and of adjustable width
• 74121 one-shot (monostable multivibrator) non-retriggerable.

Output pulse width is determined by an external RC network

One-shot

• The 74121 is non-retriggerable - it ignores input transitions when the output pulse is HIGH
• It is often more useful to use a retriggerable one-shot; e.g. 74LS122

For this type of input both behave the same

For this type:

Oscillators

This sets the threshold levels

This sets the clock period (∝ RC)

v⁺=v_o/2

v^-=v_C

Digital circuits also need clocks.

We can create a simple "relaxation oscillator" using the Schmitt trigger:

This is an astable multivibrator (no stable state)

Oscillators

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• For lowish frequencies (<1MHz), a cheap and reliable clock can be made with a 555 timer chip.

555 Timer

555 Timer

transistor acts as a voltage controlled switch that passes current from "discharge" input to ground when base voltage is HIGH

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555 Timer

Voltage divider

V_control = 2/3 Vcc

V_trig = 1/3 Vcc

555 Timer

Voltage divider

Control Voltage

V_control = V_control

V_trig = 1/2 V_control

Alternatively, we can set V_control externally:

555 Timer

Two Comparators:

Output a HIGH voltage level when the "+" input is greater than the "-" input.

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Upper comparator: Threshold input is compared to V_control

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Lower comparator: Trigger input is compared to V_trig.

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Results are passed to a flipflop

V_control

V_trig

555 Timer

Flipflop:

Stores the information of which comparator last passed it a high voltage.

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If Threshold>V_control ;

S=1

Output state is HIGH. Transistor is switched on

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If Trigger< V_trig;

R=1

Output state is LOW

Transistor is switched off.

V_control

V_trig

S

R

Q

555 Timer: Monostable configuration.�Single pulse

A

B

C

D

E

A

B

C

D

E

• Initial state: flipflop is "set". Point C is HIGH.
• Transistor is on - passing capacitor charge to ground.
• When trigger input at A goes LOW, bottom comparator triggers and E goes HIGH.
• Flipflop changes state: C goes LOW
• Transistor is off - capacitor starts charging (B) through R
• When point B reaches 2/3 Vcc, flipflop changes state, transistor is on, capacitor discharges rapidly.
• Output pulse is just the inverse of C
• Width of output pulse = 1.1×R×C

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trigger input

Capacitor voltage

FF output

upper comp.

lower comp.

555 Timer: Astable configuration

• In this mode, connect both comparator inputs to the capacitor in order to generate a clock.
• Charge up through R_A+R_B, discharge through R_B
• Capacitor charging and discharging times can be controlled by resistor selection, in order to define the clock period and duty cycle

555 Timer: Practical limits

• For reliable performance:
• The resistors R_A and R_B must be between 1kΩ and 3MΩ
• The capacitor C must be greater than 500pF
• Shortest period ~ 5×10^-7, (Max frequency f_max= 2MHz)
• If R_B>>R_A, duty cycle ~50% (square wave oscillator)
• Power supply drift is not a problem - time constant is independent of power supply - only depends upon resistor and capacitor values.
• Buffer at last stage can provide enough current to drive many TTL loads