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Agenda

Recap

ADC, fixed-point
Assembly-C mix
Lab 8: oversampling, Nyquist, calibration

Agenda

Communication
Serial: UART, interrupts
FIFO Queues used as buffers in communication
Lab 9: Distributing Lab 8

Transmitter uses ADC to read potentiometer
Receiver uses LCD to display position.
FIFO serves as buffer at receiver

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Announcements

Grading

20% Canvas quizzes (drop 1)
30% Lab
15% Exam1 average ~85
15% Exam2 average ~89
20% Final regularly scheduled

Exam 2
Final Exam (on paper, in person)
Lab 10

Freeform, 1 page proposal
5% checkout, 1% YouTube video

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EE319K/EE319H course average estimator

GradeEstimator.xlsx in folder with lectures

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Lab 8 review

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ADC0_SAC_R = 5;

// 32 ADC sample average

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Lab 8 Oversampling and Nyquist

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main2:

startTime = NVIC_ST_CURRENT_R;

Data = ADC_In(); // sample 12-bit channel 5

stopTime = NVIC_ST_CURRENT_R;

ADCtime = ((startTime-stopTime)&0x0FFFFFF)/80;

// ADCtime is ADC_In execution time in usec

ADC0_SAC_R=0 ADCtime=8us

ADC0_SAC_R=5 ADCtime=257us

Averaging improves SNR but costs time and power

Run main5 and discover the Nyquist Theorem

Oversampling: We will sample the ADC faster than we need, and average multiple samples to get one reading. This averaging, called oversampling, will improve the signal to noise ratio.

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CLT EE319H

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Central Limit Theorem: As independent random variables are added, their sum tends toward a Normal distribution. Assume the input is constant, as more and more data are added together (averaging), the pmf of the sum (or average) will tend towards a Gaussian shape.

Constant input
14-bit ADC on MSP432
Average of last N samples
f_s = 1000 Hz

Run main4 on your Lab 8 and see what you get

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Lab 10 preview

Lab 10 proposals

https://docs.google.com/document/d/1CaKjDjtigh_SSH7nRQqYKEKcgx83ilUT-1_nLLkrEqM/edit?usp=sharing

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Lab 9 Introduction

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<,d1,dot,d2,d3,d4,CR,>

Lab 8

Lab 9

0 to 2.000cm

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Lab 9 Spring 2022

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Connect PC5(out) to PC4(in)

<,d1,dot,d2,d3,SP,CR,>

0 to 2.000cm

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Introduction to Communication

Process

Encode (convert data to physical form)
Transmit (send energy across distance)
Decode (convert physical form back to data)

Layers

Transport (Example TLS)
Network

Message: <,d1,dot,d2,d3,d4,CR,>

Link

Serial: universal asynchronous receiver/transmitter

Physical

Digital: 3.3V is true, 0V is false

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https://en.wikipedia.org/wiki/OSI_model

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Physical Layer

Link Layer

Universal Asynchronous Receiver Transmitter

Serial: one bit at a time
8-bit data
Both agree on time duration for each bit (1ms)

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TxD/PC5

RxD/PC4

Gnd

RxD/PC4

TxD/PC5

Gnd

0 is 0V
1 is 3.3V

How is this different from SPI to ST7735?

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Universal Asynchronous Receiver/Transmitter (UART)

UART (Serial Port) Interface

Frame

1 start bit=0
8 data bits
1 stop bit=1

Idle

High, 3.3V

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1ms

Bit time = 1ms

Baud rate = 1000 bps

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Universal Asynchronous Receiver/Transmitter (UART)

UART (Serial Port) Interface

Bit time is the duration of each bit, 1ms
Baud rate is total number of bits per unit time

Baudrate = 1 / bit-time = 1000bps

Bandwidth is data per unit time

Bandwidth = (data-bits / frame-bits) * Baudrate = 800bps or 100 bytes/sec

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1ms

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TM4C123 LaunchPad I/O Pins

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Serial I/O

Serial communication

Transmit Data (TxD), Receive Data (RxD), and Signal Ground (SG) implement duplex communication link
Both communicating devices must operate at the same bit rate
Least significant bit sent first

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Full duplex

Half duplex

Simplex

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UART - Transmitter

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UART - Transmitter

Tx Operation

Data written to UART0_DR_R

passes through 16-element FIFO
permits small amount of data rate matching between processor and UART

Shift clock is generated from 16x clock

permits differences in Tx and Rx clocks to be reconciled

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UART - Receiver

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UART - Receiver

Rx Operation

RXFE is 0 when data are available
RXFF is 1 when FIFO is full
FIFO entries have four error bits

BE set when Tx signal held low for more than one frame (break)
OE set when FIFO is full and new frame has arrived
PE set if frame parity error
FE set if stop bit timing error

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TM4C UART Setup

UART1 operation

UART1 clock started in SYSCTL_RCGCUART_R
Digital port clock started in SYSCTL_RCGCGPIO_R
UART1_CTL_R contains UART enable (UARTEN), Tx (TXE), and Rx enable (RXE)

set each to 1 to enable
UART disabled during initialization

UART1_IBRD_R and UART_FBRD_R specify baud rate

baud rate = (bus clock frequency)/(16*divider)
ex: want 19.2 kb/s and bus clock is 8 MHz
8 MHz/(16*19.2 k) = 26.04167 = 11010.000011₂
Tx and Rx clock rates must be within 5% to avoid errors

GPIO_PORTB_AFSEL_R to choose alternate function
Write appropriate values to GPIO_PORTB_PCTL_R (See slide 4)
GPIO_PORTB_DEN_R Enable digital I/O on pins 1-0
GPIO_PORTB_AMSEL_R no Analog I/O on pins 1-0
write to UART1_LCRH_R to activate

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UART_4C123 Setup

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// Assumes a 50 MHz bus clock, creates 115200 baud rate

void UART_Init(void){

SYSCTL_RCGCUART_R |= 0x0001; // activate UART0

SYSCTL_RCGCGPIO_R |= 0x0002; // activate port B

while((SYSCTL_PRGPIO_R&0x01) == 0){};

UART0_CTL_R &= ~0x0001; // disable UART

UART0_IBRD_R = 27;

// IBRD=int(50000000/(16*115,200)) = int(27.1267)

UART0_FBRD_R = 8;

// FBRD = round(0.1267 * 64) = 8

UART0_LCRH_R = 0x0070; // 8-bit length, enable FIFO

UART0_CTL_R = 0x0301; // enable RXE, TXE and UART

GPIO_PORTB_AFSEL_R |= 0x03; // alt funct on PB1-0

GPIO_PORTB_PCTL_R =

(GPIO_PORTB_PCTL_R&0xFFFFFF00)+0x00000011;

GPIO_PORTB_DEN_R |= 0x03; // digital I/O on PB1-0

GPIO_PORTB_AMSEL_R &= ~0x03; // No analog on PB1-0

}

80MHz

PORTC

80MHz

PC5,4

UART1

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TM4C UART0 – Registers

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UART Synchronization

Busy-wait operation

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UART Busy-Wait Send/Recv

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// Wait for new input,

// then return ASCII code

uint8_t UART_InChar(void) {

while((UART0_FR_R&0x0010) != 0);

// wait until RXFE is 0

return((uint8_t)(UART0_DR_R&0xFF));

}

// Wait for buffer to be not full,

// then output

void UART_OutChar(uint8_t data) {

while((UART0_FR_R&0x0020) != 0);

// wait until TXFF is 0

UART0_DR_R = data;

}

UART1

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UART Communication

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What data is this?

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UART Interrupts

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Make it interrupt here

Transmitter 10 Hz ISR:

Toggle PF2
Measure ADC
Convert
Create message
Call OutChar 8 times

Receiver ISR:

Toggle PF1
Read entire message
Put all data into Fifo

Receiver main:

Get Fifo
Toggle PF3
Interpret
OLED output

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Summary

Bard, Erez, Cuevas, Gerstlauer, Telang, Tiwari, Valvano, Yerraballi

Summary

Communication
Physical layer – link layer
Serial: UART
Lab 9: Distributing Lab 8

Transmitter uses ADC to read potentiometer
Receiver uses LCD to display position.
FIFO serves as buffer at receiver

Next time

Serial: UART, interrupts
FIFO Queues used as buffers in communication

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