EE 198: EECS151 Tapeout

Lecture 2: “What’s an SoC”, Chipyard style!

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• General member sign-up: berkie.ee/gm-app
• No essays, no interviews, all are welcome!
• Rolling Admissions
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• Pizza and soldering at 1st general meeting (9/26, 5-7pm @ Woz!)

Member Officer Project

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IEEE: How you can join! (Quick ad)

• Committee Officer Applications: http://berkie.ee/v2zipx
• More details on the doc, join!!
• If you’re interested in leading a project, apply to Techops!
• 1st general meeting: TBD(?)
• Pull up will be fun trust 🙏

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Last Time… Introduction

All you need to pretend you read the syllabus.

• Welcome!
• Course Staff Introduction
• All Kinds of Logistics
• Welcome to BWRC! (What is BWRC?)
• Jumping right in.. What even is this “tapeout” I signed up for?
• Crash course review of EECS151
• VLSI and Hammer
• Self-introductions and discussion

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Last Week’s Actionables

• On the Github:
• Prelab 0: Git
• Lab 1A: Chipyard Setup
• Lab 1B: Chisel Bootcamp

How did it go (vibe checks~):

• Any concerns / suggestions with the Git setup?
• Did the Chipyard setup make sense?
• [Did anyone do yet] Is Chisel an “easy” language? Do you prefer Verilog?

Other questions?

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Logistics (Same as last week)

• Most up to date links, if not on website, will be on Discord
• Join the Gradescope
• Fall 2025 add code: Entry Code - NGJYBG
• https://www.gradescope.com/courses/1094924
• Lab manual & repos on Github
• https://github.com/ucb-eecs151tapeout/eecs151t-labs
• We will ask for your GitHub usernames

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Transitioning to Week 2!

• Logistics Reminders
• Class time: Friday 3-4:30pm, BWRC
• Office hours & Work sessions: TBD (For now ping us on Discord)
• Site: https://151tapeout.berkie.ee
• Discord link: berkie.ee/151t-discord
• Email: 151tapeout@ieee.berkeley.edu
• Any issues with logistics?

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Shuttle Deadline Reminder

Don’t forget - this is the big deadline for any side projects!

(You will need to complete labs quick)

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A Shuttle? What is that?

A Silicon Shuttle is a prototype service that utilizes a Multi-Project Wafer (MPW) to enable multiple customers to share masks and wafers

• allows to verify designs, prototypes, and Intellectual Property (IP) in silicon
• without incurring the high expenses associated with running test silicon
• i.e.: it’s silicon but cheap, for small projects

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Summary of Today

• Summarizing last meeting & logistics
• Assignment recap - Chisel questions?’’
• What’s an SoC? Why an SoC? Why an ASIC SoC?
• SoC Case Study: Rocket Chip, an SoC generator!
• Rocket Chip Tiles - what does a core need?
• Brief intermodule connectivity with TileLink
• EECS151 CPU Integration: First Steps
• Chisel Black Box!

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Summary of Today

• Summarizing last meeting & logistics
• Assignment recap - Chisel questions?’’
• Lecture by Prof. Bora
• What’s an SoC? Why an SoC? Why an ASIC SoC?
• SoC Case Study: Rocket Chip, an SoC generator!
• Rocket Chip Tiles - what does a core need?
• Brief intermodule connectivity with TileLink
• EECS151 CPU Integration: First Steps
• Chisel Black Box!

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Lecture by Prof. Bora!

Borivoje (Bora) Nikolic

Decal Advisor

Very Cool EECS Professor

BWRC & SLICE Labs

Borivoje Nikolic | EECS at UC Berkeley

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Questions?

​

Next: Jumping into the new stuff!

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“SoC”

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“SoC”

System-on-Chip

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What is a “System-on-Chip” (SoC)?

• “A system on a chip is an integrated circuit that compresses all of a system’s required components onto one piece of silicon”

​

Recall

Lecture 1:

(“Southbridge” and “northbridge”: pre-SoC, core logic was spread across multiple chips outside the CPU.)

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Why might we want an SoC?

• What do you think?

​

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Why might we want an SoC?

Area: less space than multiple discrete components

Power efficiency: less large components and circuits

• -> significant reduction in power consumption

Cheaper: single SoC chip may be cheaper than a set of multiple

Reliability: a single SoC has fewer connections

• -> more reliable than multipart system connected through a substrate

Performance: signals can stay on chip

• -> can achieve higher performance + speed than multipart

​

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Why might be drawbacks of an SoC?

• What do you think?

​

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Why might be drawbacks of an SoC?

Single point of failure: a failure in one component affects the entire system (which limits upgrades, too)

Time to market: designing custom SoCs requires more expertise + specialized tools than off-the-shelf components

• -> can be recouped only if the market is big enough to absorb them

Limited mixed signal (analog/digital) optimization:

• -> all components on an SoC are manufactured with a single process technology

Flexibility: An SoC has limited scope when applied for other tasks

​

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Spoiler Alert: The benefits overshadow..

• The first SoC appeared in an LCD watch in 1974 (Computer History Museum)
• Way before the Ap Watch days!
• Since 2000s, integrated WiFi, Bluetooth, Cellular in SoCs helped make smartphones a way of life
• IoT devices (wearables, smart home monitors..) benefit from SoCs’ reduced power operation
• Etc, etc..

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Spoiler Alert: The benefits overshadow..

• Fun fact: Many of the drawbacks are now being combatted with the advent of “Chiplets” (but we won’t touch upon these here)

[read more here]

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SoC ASICs

“System-on-Chip Application-Specific Integrated Circuits”

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Why do SoC ASICs? (EECS151 review!)

• These same exact topics come up in EECS151!

Recall EECS151 lectures - why pick ASIC over FPGA?

(Wawrzynek’s slides here to jog our memory)

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Why do SoC ASICs?

• EECS151 focused on the cost over volume trade-off (is still true!)
• With SoCs on FPGAs there are even more limitations:
• FPGA LUTs + fabric is “expensive” area + power wise
• The EECS151 CPU is tiny - many SoC designs can’t fit on one FPGA
• No analog block integration (the FPGA itself is digital)
• Limited clocking, network, available I/O, interfaces, etc..

J. Wawrzynek

ASIC

FPGA

EECS151 Board

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Why do SoC ASICs?

• Hence for this project, we jump straight to an ASIC SoC!
• And to the joys of verifying IP for an open-source PDK. Yay!

(intellectual property)

(i.e. existing designs)

(process development kit)

(i.e. SKY130)

(...it’s also good fun and resume-building!)

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Questions?

​

Next: our SoC is a Rocket Chip!

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SoC Case Study: Rocket Chip

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Modern SoCs are quite intense

• While we will learn to recognize their features, we are not setting out to re-create an Apple or Nvidia chip

Apple M2/MAX

67 billion transistors

Nvidia A100

54.2 billion transistors

​

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Generators - a time saver! (if they work)

• In fact, we barely have to create from scratch at all
• Industry + academia have been working on “generators” to varied success - mostly for cores - to speed up this process

https://github.com/antmicro/soc-generator

​

https://codasip.com/

​

FPGA cores

C++

Cornell Efforts..

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Aside: Analog Generators?!

• If you really want to dig into it, there’s some for analog circuits, but they tend to be less approachable + harder to implement

https://openfasoc.readthedocs.io/en/latest/

​

UCB vs UoM..

Python-based

Generators

>_>

https://bag-framework.readthedocs.io/en/latest/overview/overview.html

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A more approachable SoC: Rocket Chip

• Instead we will create a “Rocket Chip” SoC
• Rocket Chip is an open-source SoC generator
• Allows us to parametrize our designs
• Recall Lab 1b: Chisel Bootcamp..
• Has a proven research + industry record

-> now

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Dissecting a Rocket Chip

• Rocket Chip has generators for many standard SoC modules

The Rocket Chip Generator (2016 paper)

​

Core(s)

Caches

+ TLBs

(translation lookaside buffer)

RoCC

(coprocessor interface)

+ Accelerators

Tile(s) (for cache coherency)

TileLink

(protocol / network)

+ Constellation

(physical network)

Peripherals

Let’s learn more about them!

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Dissecting a Rocket Chip

• Rocket Chip has generators for many standard SoC modules

The Rocket Chip Generator (2016 paper)

​

Core(s)

Caches

+ TLBs

(translation lookaside buffer)

RoCC

(coprocessor interface)

+ Accelerators

Tile(s) (for cache coherency)

TileLink

(protocol / network)

+ Constellation

(physical network)

Peripherals

(don’t worry about all of them rn)

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Rocket Chip Tiles (And All Within)

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(Rocket Chip ->) Rocket Chip “Tile” (?)

• We can check the documentation but..
• What does it mean? What is a Rocket system? Why a Tile?
• Let’s learn to read these kinds of docs!

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(Rocket Chip ->) Rocket Chip Tile

• A Tile is a configurable processor module template
• Keep the helpful default configuration, or you can choose:
• The number & type of cores in a Tile
• The number & type of accelerators
• The organization of private caches
• The Tile design helps ensure cache-coherency - a difficult task!

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(Rocket Chip -> Rocket Tile ->) Rocket Core

​

• What’s the deal with all these Rockets?
• Note: “Rocket Chip” =/= “Rocket Chip Tile” =/= “Rocket Tile” =/= “Rocket Core”
• I’m so sorry…. don’t worry about it
• Similar to EECS151 CPU, a Rocket Core is a pipelined RISC-V core
• Except much fancier (- it was the first open source RISC-V CPU!)
• Think nothing more of it, accept the abstraction (or read the docs)

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(Rocket Tile ->) L1$ Cache(s)

​

• Recall EECS151LA Project Checkpoint 3
• Cores operate on data in memory
• The memory bits can be instructions or data
• Caches create the illusion of large memory with low latency
• In an SoC, you may see a cache hierarchy (L1$, L2$..)
• Caches can be shared or private
• Take CS152 to learn more!
• Later we will talk about physical design
• “How do SRAMs for caches work in SKY130?”

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“Rocket” Summary

• “Rocket Chip” has Rocket Chip “Tiles”
• A Tile can be parametrized and feature any core
• If it has a “Rocket Core” (RISC-V core), it is a “Rocket Tile”
• A Tile has a default of instruction and data private caches
• Which are magically (read the docs) coherent
• We will ignore accelerators & coprocessors for now..

Chip

Tile

(Rocket) Tile

Core

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“Rocket” Summary (Very Simplified)

Rocket Chip

(Generic) Tile

Rocket Tile

​

​

​

​

Rocket Core

Caches

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Rocket Chip (Less Simplified)

Your

Tile

we will talk

more about

buses / etc /

peripherals

another time

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How does this compare to “reality”?

You have access to IP that does get used in industry, and some is even pretty well known!

(BOOM as seen on prior slide)

https://www.theregister.com/2020/07/03/open_chip_hardware/

​

Basically: “Wow berkeley is cool! :D” (or read the article)

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What about the cutting edge SoCs?

Right now, you can’t quite generate a top-tier industry-quality SoC

(although you can read about them..)

https://www.reddit.com/r/ReverseEngineering/comments/pos7hb/apple_m1_crowdsourced_reverseengineering_doc/

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Maybe there’s hope(™)…

Right now, you can’t quite generate an industry**-quality core*….

…Unless you are Beijing institute of open source chip!

Where is the line between unique research and engineering might?

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You’ll notice many components are the same*

(2019 patent, parametrized

small core?)

​

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You’ll notice many components are similar*

(2013 arithmetic branch fusion patent?)

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You’ll notice many components are useful*

Point being: Berkeley will use Chipyard so often that you’ll get tired of it, BUT it is genuinely a good reference for SoCs!

(my/our bias >_>)

(2017/19 patent?)

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Back to SoC Land:

How does a Tile fit into the SoC system?

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What connects *anything* in an SoC?

(Intermodule Communication)

​

At this point, our SoC is like a Soup-on-Chip

• Tiles/Modules/Cores are floating isolated

​

What’s the point of that?

• We need some network!

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Intermodule Communication

Networking is hard!

• There are intermodule vs external interfaces
• There are many interfaces / protocols
• These have to be implemented in some physical manner

(some interfaces.. imagine trying to implement *all* of them)

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TL;DR Our Protocol: TileLink

• Rocket Chip + we (Lab 2b) will use TileLink
• “a protocol framework for describing a set of cache coherence transactions that implement a particular cache coherence policy”
• Don’t worry about the details for now (if you want to get ahead: Read The Docs )

​

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(preview) Chipyard Tiles in this network

A “Tile” in Chipyard can be thought of as a “node” in the SoC connectivity diagram and can adopt different roles

• Client node = makes requests (output)
• Manager node = responds to requests (input)
• Sub-type: register node (easy way to set up MMIO registers)
• Identity node = mirrors requests (input/output)

(In a future lecture, we will talk about interconnects + NoC.. or you can take 251B)

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Questions?

​

Next: How does this relate to our CPU?

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Great, we now know a lot about *someone else’s* RISC-V CPU (Rocket Core).

Why do we care?

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Your EECS151LA CPU is extremely similar!

• What are some key differences?

(we will explain the rest in a second)

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But also a little different..

• What are some key differences?
• Written in Verilog, not Chisel
• We need some sort of black box wrapper
• Does not have an interface to the rest of the Rocket Chip SoC
• No TileLink - what is this “TileBus”? Can we make an adapter for TileLink?
• Is not Linux-ready (but let’s ignore that for now)

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How may we fix that?

Step 1: Create a Chisel Black Box

Step 2: Create a TileLink Adapter

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Introduction to Lab 2

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Lab 1 Recap: Chipyard & Chisel Setup

• That was a lot - there are so many moving parts!
• We use Chipyard to organize all these open source tools
• That’s what you setup for Lab 1a!
• Which of these are now kind of familiar to you?

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Lab 1 Recap: Chipyard & Chisel Setup

​

• Which of these are now kind of familiar to you?
• Hopefully many!

61C

/151

Lab 1

Lecture 2

Lecture 1

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General Lab 2 Steps

• Step 1: Bring out your EECS151 CPU!
• You will need to add it to Chipyard
• Convert your EECS 151 CPU to a single Verilog file
• Don’t worry, this is not manual..
• Step 2: Black Box your Verilog in Chisel
• Time to put your Chisel knowledge to the test!

Seems simple? We’ll see!

(Goal: Lab 2 is more directed, Lab 3 will be more exploratory)

​

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What you should aim to learn from Lab 2

You will define a tile that instantiates your black box Chisel module (wrapping your verilog core), which exposes its memory interface in its io description

Your tile will contain HDL logic that maps the blackbox core memory requests to tilelink requests

Then it can play nice with other tiles on the system bus :)

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What you’ll see: Chipyard Black Box

A verilog module in a chipyard trenchcoat!

class myVerilogCore() extends BlackBox

with HasBlackBoxResource

With HasMyVerilogCoreIO {

addResource(“vsrc/mycore.v”)

}

​

A verilog blackbox

https://chipyard.readthedocs.io/en/stable/Customization/Incorporating-Verilog-Blocks.html#incorporating-verilog-blocks

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What you’ll see: MMIO

MMIO = memory-mapped IO

• Maps memory request to given address into register read/write
• Very convenient for moving control into software
• (RTL setting a register vs. memory write setting a register)

To use: add extends HasRegMap your module declaration + define a regmap

https://chipyard.readthedocs.io/en/stable/Customization/MMIO-Peripherals.html#mmio-accelerators

https://lwn.net/Articles/698014/

​

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SSH Setup Check-in

Just in case you’re getting bugs, a reminder

• You can use VS Code for more visual interactivity with Chipyard
• Use Extensions: people swear by Metals
• You can configure your SSH separately from other class accounts
• Ex: fixes double .eecs.berkeley.edu error

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EECS151LA Core Check-In

• DO NOT LEAVE TODAY WITHOUT HAVING A EECS151LA CORE - if you realized yours doesn’t work, make friends!
• How will you make friends?
• Time for our self-intro slide deck!

[Public] Self-Intros FA25!

http://berkie.ee/151t-self-intro-fa25

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Summary (Recap) of Today’s Content

• Summarizing last meeting & logistics
• Assignment recap - Setup / Chisel questions?
• Lecture by Prof. Bora
• What’s an SoC? Why an SoC? Why an ASIC SoC?
• SoC Case Study: Rocket Chip, an SoC generator!
• Rocket Chip Tiles - what does a core need?
• Brief intermodule connectivity with TileLink
• EECS151 CPU Integration: First Steps
• Chisel Black Box & TileLink Adapter

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Questions?

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Self-Intro & work session time!~

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