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1-BIT MEMORY CELL

Flip-flop is a circuit of a bi-stable type multi vibrator which has two states namely logic 0 and logic 1.
It is used to store binary data.
The output remains same until state of inputs will be changed.
(A) when A=0, (positive logic system) (i) In inverter1, Q = A'= B= 1

(ii)In inverter2, Q' = B' = A = 0

(B) when A=1, (negative logic system) (i) In inverter1, Q = A'= B= 0

(ii)In inverter2, Q' = B' = A = 1

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Some key points:�

The 2 outputs are always complementary.
The circuit has 2 stable states. when Q=1, it is Set state. when Q=0, it is Reset state.
The circuit can store 1-bit of digital information and so it is called one-bit memory cell.
The one-bit information stored in the circuit is locked or latched in the circuit. This circuit is also called Latch.

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LATCH VS FLIP-FLOP

Latch and flip-flops are basic building block of the most sequential circuits. The main difference between them is clocking mechanism that they use.
Latch is controlled by enabling signal and they are level triggered in either positive or negative level. The output state is free to change according to input values.
Flip-flop is pulse or clock edge triggered instead of level triggered, the change in inputs has no effect on the output as long as clock signal is applied.

LATCH	FLIP-FLOP
It is asynchronous.	It is synchronous.
They are basic building blocks of sequential circuits and are made from logic gates.	They are basic building blocks of sequential circuits and are built from latches.
Sensitive to level triggering.	Sensitive to edge triggering.
Output may change multiple times in given interval of time period.	Output changes at particular instant of time.

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CLOCK SIGNAL

It is a particular type of signal that oscillates between a high and a low state, produced by clock generator.
The most common clock signal is in the form of square wave.
The time required to complete on cycle is called “Clock Period”.
Circuit using the clock signal for synchronization may become active at either positive edge, negative edge, positive level negative level.
The output of a flip flop can be changed by bring a small change in the input signal. This small change can be brought with the help of a clock pulse or commonly known as a trigger pulse.
When such a trigger pulse is applied to the input, the output changes and thus the flip flop is said to be triggered.

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TRIGGERING

1. High Level Triggering- When a flip flop is required to respond at its HIGH state, a HIGH level triggering method is used. It is mainly identified from the straight lead from the clock input.

2. Low Level Triggering- When a flip flop is required to respond at its LOW state, a LOW level triggering method is used. It is mainly identified from the clock input lead along with a low state indicator bubble.

1 & 2 are also known as

Gated Latch or level triggered

flip flop.

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3. Positive Edge Triggering- When a flip flop is required to respond at a LOW to HIGH transition state, POSITIVE edge triggering method is used. It is mainly identified from the clock input lead along with a triangle.

4. Negative Edge Triggering- When a flip flop is required to respond during the HIGH to LOW transition state, a NEGATIVE edge triggering method is used. It is mainly identified from the clock input lead along with a low-state indicator and a triangle.

3 & 4 are also known

as Clocked Flip flop.

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FLIP-FLOP

Flip flop is basic building block of synchronous sequential circuit which is built from Latches.
It has two stable states: SET & RESET, hence it is also known as 1-bit memory cell which stores either 0 or 1 as soon as input condition is changed and clock pulse is applied.
A clock generator is a device that generates a signal that periodically cycles between a high state “1” and a low state “0”.
In edge triggered flip flop, such clock signal is applied to Flip flop.
It is possible to design flip flop which responds to either any instant of the clock pulse. Based on these, flip flops can be classified as:
Positive Level Triggered Flip flops (Positive level Gated Latch)
Negative Level Triggered Flip flops (Negative level Gated Latch)
Positive Edge Triggered Flip flops
Negative Level Triggered Flip flops

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DIFFERENT TYPES OF FLIP FLOPS

SR flip flop
D flip flop
JK flip flop
T flip flop
Master Slave JK flip flop

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APPLICATION OF FLIP FLOPS

Data storage and tranfer.
Registers
Counters
Memory
Bounce elimination switch
Frequency division

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SR FLIP FLOP – SYMBOL

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SR FLIP FLOP USING NOR GATES

LOGIC DIAGRAM

TRUTH TABLE

S	R	Q	Q’	STATE
0	0	Q	Q’	No change
0	1	0	1	Reset
1	0	1	0	Set
1	1	0	0	Indeterminate

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SR FLIP FLOP USING NAND GATES

LOGIC DIAGRAM

TRUTH TABLE

S	R	Q	Q’	STATE
0	0	Race	Race	Race
0	1	0	1	Reset
1	0	1	0	Set
1	1	No Change	No Change	Inactive

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POSITIVE EDGE TRIGGERED SR FLIP FLOP

LOGIC DIAGRAM

TRUTH TABLE

INPUTS			OUTPUTS		REMARKS
CLK	S	R	Q	Q’	REMARKS
0	×	×	Q	Q’	No Change (NC)
1	×	×	Q	Q’	No Change (NC)
	×	×	Q	Q’	No Change (NC)
	0	0	Q	Q’	No Change (NC)
	0	1	0	1	Reset
	1	0	1	0	Set
	1	1	Race	Race	Avoid

FF is disabled

FF responds only to positive edges

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NEGATIVE EDGE TRIGGERED SR FLIP FLOP

LOGIC DIAGRAM

TRUTH TABLE

INPUTS			OUTPUTS		REMARKS
CLK	S	R	Q	Q’	REMARKS
0	×	×	Q	Q’	No Change (NC)
1	×	×	Q	Q’	No Change (NC)
	×	×	Q	Q’	No Change (NC)
	0	0	Q	Q’	No Change (NC)
	0	1	0	1	Reset
	1	0	1	0	Set
	1	1	Race	Race	Avoid

FF is disabled

FF responds only to negative edges

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DRAWBACK OF SR FLIP FLOP

When S=R=0 or S=R=1, the outputs Q and Q’ either don’t change (NC) or they indeterminate (Invalid) due to race condition.
This disadvantage of SR latch can be overcome by using the gated D latch.

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D FLIP FLOP- SYMBOL

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D-FLIP FLOP�POSITIVE EDGE TRIGGERED D FLIP FLOP

LOGIC DIAGRAM

TRUTH TABLE

INPUTS		OUTPUTS		REMARKS
CLK	D	Q	Q’	REMARKS
0	×	Q	Q’	No Change (NC)
1	×	Q	Q’	No Change (NC)
	×	Q	Q’	No Change (NC)
	0	0	1	Q follows D input
	1	1	0	Q follows D input

FF disabled

FF responds only on positive edges

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D-FLIP FLOP�NEGATIVE EDGE TRIGGERED D FLIP FLOP

LOGIC DIAGRAM

TRUTH TABLE

INPUTS		OUTPUTS		REMARKS
CLK	D	Q	Q’	REMARKS
0	×	Q	Q’	No Change (NC)
1	×	Q	Q’	No Change (NC)
	×	Q	Q’	No Change (NC)
	0	0	1	Q output follows D input
	1	1	0	Q output follows D input

FF disabled

FF responds only on negative edges

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ADVANTAGES, DISADVANTAGES AND APPLICATIONS OF D FLIP FLOP

ADVANTAGES:

They are simple and the fact that the output and input are essentially identical, except displaced in time by one clock period.

DISADVANTAGES:

A delay flip flop in a circuit increases the circuit’s size, often to about twice the normal. Additionally, they also make the circuits more complex.

APPLICATIONS:
As a delay element.
Used in digital registers and counters.

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JK FLIP FLOP�POSITIVE EDGE TRIGGERED JK FLIP FLOP

LOGIC DIAGRAM

TRUTH TABLE

CASE	INPUTS			OUTPUTS		REMARKS
CASE	CLK	J	K	Q	Q’	REMARKS
1	0 or 1	×	×	NC	NC	FF is disabled
2		×	×	NC	NC
3		0	0	NC	NC
4		0	1	0	1	Reset
5		1	0	1	0	Set
6		1	1	Q’	Q	Toggle

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NEGATIVE EDGE TRIGGERED JK FLIP FLOP

LOGIC DIAGRAM

TRUTH TABLE

INPUTS			OUTPUTS		REMARKS
CLK	J	K	Q	Q’	REMARKS
0 or 1	×	×	Q	Q’	No Change (FF is disabled)
	×	×	Q	Q’	No Change (FF is disabled)
	0	0	Q	Q’	No Change
	0	1	0	1	Reset
	1	0	1	0	Set
	1	1	Q’	Q	Toggle

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APPLICATIONS OF JK FF

Shift registers
Counters

COMPARISON OF SR AND JK FF

SR NO	PARAMETERS	SR FF	JK FF
1	No. of inputs	Two	Two
2	Invalid state	SR=11	No invalid state
3	Race condition	SR=11	Race is avoided
4	Toggling	Does not take place	Takes place for JK=11

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TOGGLE (T) FLIP FLOP�POSITIVE EDGE TRIGGERED T-FF

LOGIC DIAGRAM

TRUTH TABLE

INPUTS		OUTPUTS		REMARKS
CLK	T	Q	Q’	REMARKS
	0	Q	Q’	No Change (NC)
	×	Q	Q’	No Change (NC)
1	×	Q	Q’	No Change (NC)
0	×	Q	Q’	No Change (NC)
	1	Q’	Q	Toggle

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TOGGLE (T) FLIP FLOP�NEGATIVE EDGE TRIGGERD T-FF

LOGIC DIAGRAM

TRUTH TABLE

INPUTS		OUTPUTS		REMARKS
CLK	T	Q	Q’	REMARKS
×	0	Q	Q’	No Change (NC)
	1	Q	Q’	No Change (NC)
0	1	Q	Q’	No Change (NC)
1	1	Q	Q’	No Change (NC)
	1	Q’	Q	Toggle

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APPLICATION OF T FF

Acts as basic building block of a ripple counter.
For frequency division.
For producing 180˚out of phase signals.

COMPARISON OF D AND T FF

SR NO	PARAMETERS	D FF	T FF
1	No. of inputs	One	One
2	Output	Follows the input	Toggles when input is 1
3	Derived from	SR FF	JK FF
4	Presence of inverter	Present	Absent
5	Clock frequency division	Does not take place	Takes place

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MASTER SLAVE JK FF

Logic Diagram

Truth-table

CASE	INPUTS			OUTPUTS		REMARKS
CASE	CLK	J	K	Q	Q’	REMARKS
1	×	0	0	Q	Q’	No Change (NC)
2		0	0	Q	Q’	No Change (NC)
3		0	1	0	1	Reset
4		1	0	1	0	Set
5		1	1	Q’	Q	Toggle