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Silvia Zorzetti

Design and Engineering of Modern Beam Diagnostics, USPAS 2024

FPGA based beam instrumentation

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What is a VLSI?

  • “Very large-scale integration (VLSI) is the process of integrating or embedding hundreds of thousands of transistors on a single silicon semiconductor microchip. VLSI technology was conceived in the late 1970s when advanced level computer processor microchips were under development.”

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  • VLSI initially designed to support hundreds of thousands of transistor gates on a microchip which
  • As of 2012, exceeded several billion. All of these transistors are remarkably integrated and embedded within a microchip
  • Moore’s law: Number of transistor density in an Integrated Circuit doubles every two year.

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IC Technology

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IC Technology

Full custom (VLSI)

Semi-custom

ASIC

Gate Array

Stand. cell

PLD

PAL

PLA

FPGA

TECHNOLOGY TRADEOFF

Choose the optimal compromise between design tools (development costs) and technology (production costs)

  • Technology maturity
  • Flexibility
  • Performances (speed, area, time to market)

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IC Technology – Full custom

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FULL CUSTOM DESIGN

  • Placing the transistors -> minimum size
  • Routing and wiring among the transistors to optimize the signal transmission
  • Custom mask layers
  • For very high performances systems

IC Technology

Full custom (VLSI)

Semi-custom

ASIC

Gate Array

Stand. cell

PLD

PAL

PLA

FPGA

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IC Technology – Semi custom

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ASIC

  • Lower layers already built

Gate Array

  • Completed chip of gate array, except the metal connections are missing

Standard cells

  • Library of logic gates and functions

IC Technology

Full custom (VLSI)

Semi-custom

ASIC

Gate Array

Stand. cell

PLD

PAL

PLA

FPGA

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IC Technology - PLD

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PROGRAMMABLE LOGIC DEVICES

  • Internal switches to allow flexible configuration
  • By changing the switches configuration different functions can be implemented

IC Technology

Full custom (VLSI)

Semi-custom

ASIC

Gate Array

Stand. cell

PLD

PAL

PLA

FPGA

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PLD: PAL and PLA

PAL

PLA

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PROS

  • Simple design
  • Cheap
  • Fast

CONS

  • Limited number of inputs
  • Less flexibility

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Field Programmable Gate Array - FPGA

Pre-fabricated devices that can be electrically programmed to implement different digital circuits and systems

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  • PROS compared to the ASIC
    • Flexibility: fast configuration and reconfiguration
    • Cheaper solutions – for small volumes
    • Low development cost
    • Faster time to market
  • CONS compared to the ASIC
    • Not for mass production
    • Larger power consumption
    • Integration
  • Advanced FPGA features
    • Advanced IO standard protocols
    • Digital Signal Processing (DSP)
    • Intellectual property (IP)
    • Embedded processors (hardware and software)

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FPGA architecture

  • Field Programmable Gate Array
    • Matrix of reconfigurable gate array
  • Configurable Logic Blocks (CLB)
    • Programmable blocks for logic functions implementations
    • Arranged in the 2D matrix
  • Switch Blocks (SB)
    • Programmable routing
    • Connect the logic blocks
    • Arranged in the 2D matrix
  • IO Blocks
    • Connected to both the logic and the routing blocks
    • Arranged at the periphery of the grid
  • The structure may vary between manufacturer and product family

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CLB

SB

IOB

Cofer, R.C., Harding, B.: Rapid System Prototyping with FPGAs: Accelerating the Design Process. Newnes (2005)

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FPGA architecture – Logic and IO blocks

  • Generic logic block
    • N-input Look Up Table (LUT)
    • Flip flop for timing
    • MUX for signal routing
  • LUT
    • Implement any logic function with N-input
    • Constant delay despite the function
  • CLB
    • Group of slices

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Cofer, R.C., Harding, B.: Rapid System Prototyping with FPGAs: Accelerating the Design Process. Newnes (2005)

  • IOB
    • Programmable IO
    • Registered or Unregistered
    • Tri-state option
    • Differential or single ended
    • Different types of IO standards, e.g. LVTTL (single-ended), LVDL (differential)

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FPGA architecture – Signal Routing

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  • Horizontal and vertical routing channels

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  • Routing switches
    • Placed on each column and row of each CLBs
    • 90 or 180-degree connections between routing channels
  • Carry chain logic
    • To build larger and more efficient arithmetic functions

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FPGA architecture – Routing delay

Clock delays

  • Skew: static variation due to path length
  • Jitter: cycle varying; e.g. PLL and oscillators

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Design constrains

  • Routing delays: switches and wiring path
  • Global path constrains: system clock
  • Local path constrains. e.g. ensuring that the maximum clock delay and data path delay do not exceed the specified constrain offset

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FPGA design flow: design entry and synthesis

Design entry

  • Schematic based
  • Hardware Description Language (HDL)
  • Combined schematic and HDL
  • HDLs represent a level of abstraction that can isolate the designers from the details of the hardware implementation.
  • Schematic based entry gives designers much more visibility into the hardware.

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Synthesis

  • translates VHDL or Verilog code into a device netlist
  • check code syntax and analyze the hierarchy of the design which ensures that the design is optimized for the design architecture, the designer has selected.

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www.vlsi-world.com

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Design Entry

  • Design entity
    • Declaration: external interface
    • Body: internal description (behavioral, structure or both)
      • Not a sequential language

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Declaration

Body

Libraries

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Design Entry (cont.)

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FULL ADDER

Entity declaration

Component declarations

  • Behavioral description in a separate file

Internal signals declaration declaration

Components instantiation and interconnections

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FPGA design flow – Implementation

Implementation

  • Translate
    • combines all the input netlists and constraints to a logic design file
    • Assign the ports in the design to the physical elements
    • Design constraints
  • Map
    • Sub blocks that fit the FPGA CLB and IOB
    • Return a file with the physical representation of the design
  • Place and Route
    • Place and Route the logic blocks to meet the constraints
  • Device programming
    • Format so that the FPGA can accept it.
    • .bit file to program the FPGA

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www.vlsi-world.com

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FPGA design flow – Design verification

Behavioral Simulation (RTL Simulation)

  • Verify the logic function
  • Performed in VHDL or Verilog designs
  • Observe signal and variables
  • This is a very fast simulation and allows the designer to change the HDL code if the required functionality is not met with in a short time period.

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www.vlsi-world.com

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FPGA design flow – Design verification

Functional simulation (Post Translate Simulation)

    • Information about the logic operation of the circuit.
    • Verify the functionality of the design after the Translate process.

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Static Timing Analysis

    • Post MAP timing report
    • Lists signal path delays of the design
    • Post Place and Route timing report incorporates timing delay information to provide a comprehensive timing summary of the design
    • Critical paths

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www.vlsi-world.com

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Advanced FPGA features – DSP blocks

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Digital Signal Processing (DSP) dedicated blocks

  • Speed and flexibility improvements
  • DSP functions include adders, accumulators, coefficient register storage and multipliers
  • Implement functions such as filtering (FIR), video processing, FFT…

NEVER UNDERESTIMATE:

  • Signal routing
  • Clock distribution

Stratix V from Altera: each variable-precision DSP block can be configured using a 27x27-bit multiplier

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Advanced FPGA features - IP

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Intellectual Property (IP) cores

  • Logic blocks previously designed and customizable by the user
  • Users can create IPs

Xilinx IP for FIR compiler

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Advanced FPGA features – Embedded processors (1)

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Embedded systems 

A combination of hardware and software where software is usually known as firmware that is embedded into the hardware.

  • Real time operating system
  • Interface with external devices
  • Perform specialized operations and repeat them in time

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Advanced FPGA features – Embedded processors (2)

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Implement a small processor using the FPGA resources

  • Instantiated as an IP
  • Pre-generate hardware that can be used for embedded applications (e.g. imaging)
  • CPU cores
  • Memory interface
  • DSP functions
  • PLL for the clock input signal
    • Clock distribution
  • Write/Read registers
    • Buttons and LED
    • IO Data streaming
  • Interface with external devices

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Beam Instrumentation Digitizer

  • ADC
    • Analogue to Digital Converter
  • DAC
    • Digital to Analogue converter
  • Flash memory
    • Load the firmware in the FPGA
  • Clock generator
    • Control clock rate, phase and other parameters
  • SDRAM
    • Memory for the data flow
  • VMEbus
    • Communication protocol

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FPGA

ADC

SDRAM

VME

Clock gen

Flash mem

DAC

Hardware

FPGA

CPU

Control

User

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Compilation report

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FPGA Hardware Map

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CLB

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Embedded system

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Register Controls and Test Points

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Digital Damper Control Interface

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More FPGA boards

  • Companies like NI and Keysight offer modular programmable digitizers
    • Pre-compiled libraries and control scripts
    • Synchronization in the same crate
    • Commercial boards up to 500Msa, 14bit ADC
    • Restrictions in the hardware programming

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