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BRANCH-E & TC ENGG

SUBJECT-MICROPROCESSOR & MICROCONTROLLER

CHAPTER-6-MICROCONTROLLER

TOPIC-ARCHITECTURE OF 8086 MICROCONTROLLER

SEM-4^TH

FACULTY-ER. P PANIGRAHI (LECT. E & TC ENGG DEPARTMENT)

AY-2021-2022, SUMMER-2022

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8086 MICROCONTROLLER

Block diagram of 8086

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Software Model of the 8086 Microprocessors

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8086 Registers

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General Purpose Registers

• Normally used for storing temporary results
• Each of the registers is 16 bits wide (AX, BX, CX, DX)
• Can be accessed as either 16 or 8 bits AX, AH, AL

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AX - the Accumulator

BX - the Base Register

CX - the Count Register

DX - the Data Register

General Purpose Registers

• AX
• Accumulator Register
• Preferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language Code
• Must be used in multiplication and division operations
• Must also be used in I/O operations

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• BX
• Base Register
• Also serves as an address register

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General Purpose Registers

• CX
• Count register
• Used as a loop counter
• Used in shift and rotate operations

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• DX
• Data register
• Used in multiplication and division
• Also used in I/O operations

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Pointer and Index Registers

• All 16 bits wide, L/H bytes are not accessible

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• Used as memory pointers
• Example: MOV AH, [SI]
• Move the byte stored in memory location whose address is contained in register SI to register AH

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• IP is not under direct control of the programmer

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Flag Register

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Carry

Parity

Auxiliary Carry

Zero

Overflow

Direction

Interrupt enable

Trap

Sign

6 are status flags

3 are control flag

8086 Programmer’s Model

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ES

CS

SS

DS

IP

AH

BH

CH

DH

AL

BL

CL

DL

SP

BP

SI

DI

FLAGS

AX

BX

CX

DX

Extra Segment

Code Segment

Stack Segment

Data Segment

Instruction Pointer

Accumulator

Base Register

Count Register

Data Register

Stack Pointer

Base Pointer

Source Index Register

Destination Index Register

_{BIU registers}

_{(20 bit adder)}

_{EU registers}

The Stack

• The stack is used for temporary storage of information such as data or addresses.
• When a CALL is executed, the 8086 automatically PUSHes the current value of CS and IP onto the stack.
• Other registers can also be pushed
• Before return from the subroutine, POP instructions can be used to pop values back from the stack into the corresponding registers.

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The Stack

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INTEL 8086 - Pin Diagram

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INTEL 8086 - Pin Details

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Ground

Clock

Duty cycle: 33%

Power Supply

5V ± 10%

Reset

Registers, seg regs, flags

CS: FFFFH, IP: 0000H

If high for minimum 4 clks

INTEL 8086 - Pin Details

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Address/Data Bus:

Contains address bits A₁₅-A₀ when ALE is 1 & data bits D₁₅ – D₀ when ALE is 0.

Address Latch Enable:

When high, multiplexed address/data bus contains address information.

INTEL 8086 - Pin Details

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INTERRUPT

Non - maskable interrupt

Interrupt request

Interrupt acknowledge

INTEL 8086 - Pin Details

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Direct Memory Access

Hold acknowledge

Hold

INTEL 8086 - Pin Details

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Address/Status Bus

Address bits A₁₉ – A₁₆ & Status bits S₆ – S₃

INTEL 8086 - Pin Details

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Bus High Enable/S7

Enables most significant data bits D₁₅ – D₈ during read or write operation.

S₇: Always 1.

BHE#, A₀:

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0,0: Whole word (16-bits)

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0,1: High byte to/from odd address

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1,0: Low byte to/from even address

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1,1: No selection

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INTEL 8086 - Pin Details

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Min/Max mode

Minimum Mode: +5V

Maximum Mode: 0V

Minimum Mode Pins

Maximum Mode Pins

Minimum Mode- Pin Details

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Maximum Mode - Pin Details

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Status Signal

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Inputs to 8288 to generate eliminated signals due to max mode.

S2 S1 S0

000: INTA

001: read I/O port

010: write I/O port

011: halt

100: code access

101: read memory

110: write memory

111: none -passive

Maximum Mode - Pin Details

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DMA Request/Grant

Lock Output

Lock Output

Used to lock peripherals off the system

Activated by using the LOCK: prefix on any instruction

Maximum Mode - Pin Details

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Queue Status

Used by numeric coprocessor (8087)

QS1 QS0

00: Queue is idle

01: First byte of opcode

10: Queue is empty

11: Subsequent byte of opcode

Minimum Mode 8086 System

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Minimum Mode 8086 System

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‘Read’ Cycle timing Diagram for Minimum Mode

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‘Write’ Cycle timing Diagram for Minimum Mode

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Maximum Mode 8086 System

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Maximum Mode 8086 System

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Maximum Mode 8086 System

• Here, either a numeric coprocessor of the type 8087 or another processor is interfaced with 8086.
• The Memory, Address Bus, Data Buses are shared resources between the two processors.
• The control signals for Maximum mode of operation are generated by the Bus Controller chip 8788.
• The three status outputs S0*, S1*, S2* from the processor are input to 8788.
• The outputs of the bus controller are the Control Signals, namely DEN, DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE etc.

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Memory Read timing in �Maximum Mode

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Memory Write timing in �Maximum Mode

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8086 Control Signals

1. ALE
2. BHE
3. M/IO
4. DT/R
5. RD
6. WR
7. DEN

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Coprocessor and Multiprocessor configuration�

• Multiprocessor Systems refer to the use of multiple processors that executes instructions simultaneously and communicate with each other using mail boxes and Semaphores.

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• Maximum mode of 8086 is designed to implement 3 basic multiprocessor configurations:

1. Coprocessor (8087)

2. Closely coupled (8089)

3. Loosely coupled (Multibus)

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Coprocessor and Multiprocessor configuration�

• Coprocessors and Closely coupled configurations are similar in that both the 8086 and the external processor shares the:

- Memory� - I/O system� - Bus & bus control logic� - Clock generator

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Coprocessor / Closely Coupled Configuration

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TEST pin of 8086

• Used in conjunction with the WAIT instruction in multiprocessing environments.
• This is input from the 8087 coprocessor.
• During execution of a wait instruction, the CPU checks this signal.
• If it is low, execution of the signal will continue; if not, it will stop executing.

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Coprocessor Execution Example

Coprocessor cannot take control of the bus, it does everything through the CPU�

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Closely Coupled Execution Example

• Closely Coupled processor may take control of the bus independently.

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• Two 8086’s cannot be closely coupled.

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Loosely Coupled Configuration

• has shared system bus, system memory, and system I/O.
• each processor has its own clock as well as its own memory (in addition to access to the system resources).
• Used for medium to large multiprocessor systems.
• Each module is capable of being the bus master.
• Any module could be a processor capable of being a bus master, a coprocessor configuration or a closely coupled configuration.

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Loosely Coupled Configuration

• No direct connections between the modules.
• Each share the system bus and communicate through shared resources.
• Processor in their separate modules can simultaneously access their private subsystems through their local busses, and perform their local data references and instruction fetches independently. This results in improved degree of concurrent processing.
• Excellent for real time applications, as separate modules can be assigned specialized tasks

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Advantages of Multiprocessor Configuration

1. High system throughput can be achieved by having more than one CPU.
2. The system can be expanded in modular form.

Each bus master module is an independent unit and normally resides on a separate PC board. One can be added or removed without affecting the others in the system.

• A failure in one module normally does not affect the breakdown of the entire system and the faulty module can be easily detected and replaced
• Each bus master has its own local bus to access dedicated memory or IO devices. So a greater degree of parallel processing can be achieved.

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WAIT State

• A wait state (T_w) is an extra clocking period, inserted between T2 and T3, to lengthen the bus cycle, allowing slower memory and I/O components to respond.

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• The READY input is sampled at the end of T2, and again, if necessary in the middle of Tw. If READY is ‘0’ then a Tw is inserted.

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8086 System Memory Circuitry

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1. Minimum Mode System Memory Circuitry

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• Maximum Mode System Memory Circuitry

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Minimum Mode System Memory Circuitry

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Maximum Mode System Memory Circuitry

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THANK YOU