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sBerti: Enhancing Berti with a Smart Stride Prefetcher for Better Coverage

Jiapeng Zhou, Ben Chen, Kunlin Li, Yun Chen^*

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February 1, 2026

4th Data Prefetching Championship 2026

The Hong Kong University of Science and Technology (Guangzhou)

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Challenges & Opportunities

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February 1, 2026

New Traces from Graph, Google Traces v2 and AI-ML workloads

A prefetcher may excel on certain workloads (e.g., SPEC17) while degrading performance on others (e.g., AI-ML).
Finding new patterns not covered by existing prefetchers

New configuration: Limited bandwidth

Mechanisms for the prefetcher to automatically self-regulate based on real-time bandwidth

It has been 7 years since the last DPC event. In DPC4, three kinds of new traces are introduced. There is also a larger storage budget and a new configuration of limited bandwidth. This brings new challenges and opportunities.

Firstly, a prefetcher should strike a balance between different patterns of applications from different categories. Typically, a prefetcher modification can increase the IPC of some workloads while degrading others. As more traces are introduced, we should consider the impact on applications in more categories when making changes. Additionally, the newly introduced limited bandwidth configuration requires us to throttle prefetches based on real-time bandwidth and make the prefetches accurate.

There is also an opportunity to profile and analyze memory access patterns for the new traces. Prefetchers which performed the best in previous contests may fall short on new traces. Our strategy is to find patterns not covered by the baseline prefetchers and incorporate a light-weight prefetcher targeting the missing patterns. We hope the profiling and analysis will provide some insights to the community.

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Profiling the baseline (L1 Berti + L2 Pythia)

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Miss rate analysis

High L1D miss rate for AI-ML and Graph workloads
High L1I miss rate for GTraces v2

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Profiling the baseline (L1 Berti + L2 Pythia)

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L1D memory access trace analysis

Graph workloads: A[B[i]] accesses due to its CSR graph format

No load values in the traces and the prefetcher is not allowed to get the values in the Cache

AI-ML workloads: Stream access pattern (especially llama2.c)

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Dive into the DPC3 Berti used in baseline

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Accurate in predicting stream accesses
Misses occur every 4K page -> Missing cross-page prefetch opportunities

Time

Address

PF issued

Hit & PF useful

Miss

Incorporate stride prefetchers to cover the cross-page misses

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Smart Stride Prefetcher

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February 1, 2026

A stride prefetcher derived from the xs_stride prefetcher in XiangShan
Confidence directed stride pattern detection for accuracy
Depth adjustment based on late detection for timeliness
Strides are detected at multiples of the Delta to mitigate the OoO effect

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sBerti = Berti + Smart Stride Prefetcher

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February 1, 2026

Useful prefetches: 846 -> 995

Berti in DPC3

sBerti

PF issued

Hit & PF useful

Miss

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Can vBerti cover the cross-page pattern?

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February 1, 2026

Observation

Prefetch Queue is full most of the time. Prefetches with large strides (depth) are less likely issued.
The highest confidence is observed with stride 1.
Addresses in Prefetch Queue are stall

Still debuging on the issues

vBerti

PF issued

Hit & PF useful

As some of the reviewers have asked, since the vBerti published in MICRO prefetches using vitual addresses, can vBerti cover the cross-page pattern? Theoretically, the virtual address used in vBerti can handle this cross-page pattern. However, the vBerti does not work well in our experimental setup. It is unclear whether this is an implementation error or a theoretical flaw.

Here I will show some observations. As the memory access snippet for vBerti on llama2.c workload on the right, the prefetch depth of vBerti is always 1 and the prefetch is not timely. By profiling, we observed that the prefetch queue of vBerti is full most of the time, which makes prefetches with larger stride less likely to be issued. We also observed that stride 1 always has the highest confidence and is close to the maximum threshold. The prefetch requests in the prefetch queue are usually stall, which means late prefetches.

Although we are still debugging vBerti, theoretically, it should be capable of covering cross-page patterns.

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sBerti Storage Overhead

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February 1, 2026

Smart Stride Prefetcher: ~4KB

Stride detection table and a deduplication buffer

Berti: ~28KB

Reduce the number of the Recorded Pages to satisfy the 32KB budget in total

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sBerti Coverage in FullBW

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February 1, 2026

Slight L1D coverage increase for AI-ML and SPEC17 workloads

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sBerti Accuracy in FullBW

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February 1, 2026

Accuracy drop across all categories

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sBerti Speedup over Berti

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IPC speedup on workloads with over 50% stream access patterns

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Speedup over baseline (Berti + Pythia)

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Our solution: L1 sBerti + L2 Pythia
Slight performance gains on AI-ML(7%) and SPEC17(2%) workloads under FullBW configuration
Remain identical performance under LimitBW configuration

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Conclusion

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February 1, 2026

sBerti is a hybrid prefetcher of Berti and a Stride Prefetcher derived from XiangShan
sBerti optimizes the cross-page weakness of Berti in DPC3 and achieves ~7% speedup for AI-ML workloads
Future Work

Further optimization on sBerti for prefetch accuracy
Investigating vBerti to solve cross-page boundary problems

Special thanks to the reviewers for their constructive comments and to the DPC-4 organizers for their excellent work

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sBerti: Enhancing Berti with a Smart Stride Prefetcher for Better Coverage�Jiapeng Zhou, Ben Chen, Kunlin Li and Yun Chen. DPC4.

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February 1, 2026

Thanks for your attention!�Questions?

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Debug log of vBerti

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Debug log of vBerti

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