COA Lab Project (2016-17) �The LNMIIT, Jaipur�
Smart Home
Kartik Agrawal (15UCS060)
Harsh Bhambhani (15UCS045)
Mrinal Malik(15UCS075)
Kartikey Pohani (15UCS062)
Introduction
Functions
Memory Model
Registers
29 General Purpose Registers which are used for storing permanent values for comparison as well as temporary values and memory addresses. These can be represented by using numbers through 00000-11100, eg. R0 = 00000, R1 = 00001, R2 = 000010….
Permanent values to be stored:
R0 – Password
R1 – Break down Temp
R2 – Gas conc.
R3 – Persons / tubelight
R4 – Current Time
R5 – Time slot
R6– Music 1
R7 – Music 2
R8 – Music 3
R9 – Music 4
R10 – Desired O2 level
R11 – Current Season
R12 – Max. Tubelights
Registers R13 – R28 will be used to store temporary values as well as memory addresses.�These general purpose registers are completely interchangeable, i.e. the compiler can use R2 to store a temporary / permanent value, but it can equally well use R28.�But use of some registers is pre-defined to avoid any confusion and loss of data by the CPU.
Registers
3 Special Purpose Registers are also available that hold various miscellaneous bits that are needed by the CPU.
The flag register (Program Status Word Register) has the following typical condition code bits -
Instruction Format
Instruction Format | Description |
MOV R1, R2 | Copies content of R1 into R2 |
LDB @R1, R2 | Load value stored at memory address indicated by R1 into R2 |
STB @R1, R2 | Store the value contained in R2 at memory address indicated by R1 |
CMP R1, R2 | Compares the values in R1 and R2 and sets the flag register correspondingly |
SWP R1, R2 | Swaps the values in the R1 and R2 |
ADD R1, R2 | Adds the values stored in R1 and R2 and stores the result in R1 |
AND R1, R2 | Logical AND of R1 and R2 |
OR R1, R2 | Logical OR of R1 and R2 |
LDBI @R1, R2 | Loads value stored at address indicated by R1 into R2 and increments R1 by 1. |
1. Two Address instructions
Instruction Format
Instruction Format | Addresses |
INC R1 | Increments value in R1 by 1 |
DEC R1 | Decrements value in R1 by 1 |
JGE $L1 | Jumps if greater than 0 |
JMP $L1 | Jumps unconditionally |
JLE $L1 | Jumps if less than 0 |
JZR $L1 | Jumps if Z flag is set |
CAL $L1 | Calls subroutine |
CLR R1 | Clears the contents of R1 |
2. One Address instructions
Instruction Format
3. Zero Address instructions
Instruction | Description |
HLT | Halts the program |
PSH | Pushes the value to the top of the stack |
POP | Pops out the value from the top of the stack. |
Instruction Design
Instruction Types
2. Dyadic Operations : These combine two operands to produce a result.
ADD, SUB, MUL, DIV, CMP, AND, OR etc.
3. Monadic Operations: Monadic operations have one operand and produce one result.
CLR, INC, DEC, PSH, POP etc.
Instruction Types
4. Comparisons and Conditional Branching:
JMP , JNQ , JEQ ,JNZ ,JGT ,JLT , CMP
5. Procedure Call Instructions: These are nothing but used for calling subroutines, which are otherwise known as procedures.
Data Types
1 | 1 | 0 | 1 |
0 | 1 | 1 | 1 |
1 | 0 | 1 | 0 |
1 | 0 | 0 | 1 |
1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
Addressing Modes
Flow of Control Handling
Datapath- Single Bus Architecture
Datapath is a
collection of functional
units, such as
arithmetic logic units
or multipliers, that
perform data
processing operations,
registers, and buses.
Along with the control
unit it composes the
central processing unit
(CPU).
Arithmetic Logical�Unit (ALU)
Value of X (X2 X1 X0) | Operation |
000 | Addition |
001 | Subtraction |
010 | Multiplication |
011 | Division |
100 | Modulo |
An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic operations. It represents the fundamental building block of the central processing unit (CPU) of a computer.
ADDI R1, R2, Im
PCin | PCout | MARin | READ | SELECT4 | ADD | Zin | Zout | WMFC | IRin | R1in | R2out | DCout | Yin | SelectY | MDRout |
0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
SUBI R1, R2, Im
PCin | PCout | MARin | READ | SELECT4 | ADD | Zin | Zout | WMFC | IRin | R1in | R2out | DCout | Yin | SelectY | MDRout |
0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
SUB |
0 |
0 |
0 |
0 |
1 |
0 |
MULI R1, R2, Im
PCin | PCout | MARin | READ | SELECT4 | ADD | Zin | Zout | WMFC | IRin | R1in | R2out | DCout | Yin | SelectY | MDRout |
0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
MUL |
0 |
0 |
0 |
0 |
1 |
0 |
DIVI R1, R2, Im
PCin | PCout | MARin | READ | SELECT4 | ADD | Zin | Zout | WMFC | IRin | R1in | R2out | DCout | Yin | SelectY | MDRout |
0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
DIV |
0 |
0 |
0 |
0 |
1 |
0 |
MODI R1, R2, Im
PCin | PCout | MARin | READ | SELECT4 | ADD | Zin | Zout | WMFC | IRin | R1in | R2out | DCout | Yin | SelectY | MDRout |
0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
MOD |
0 |
0 |
0 |
0 |
1 |
0 |
COMPI R1, Im
MOVI R1, Im
ADD R1, R2
MUL R1, R2
COMP R1, R2
MOV R1, R2
JMP L1
JEQ L1
JLT L1
JGT L1
INC R1
DEC R1
THE END