Embedded ML Models

Update — Week 3

Afnan, Shlok, Dhruv

Update — Week 3

• Configured ZedBoard FPGA and booted into Linux
• Brought up the Zynq board over UART serial console
• Filesystem mounts, static IP, and network/SSH daemons all come up cleanly
• Trained MNIST model and tested prototype in Verilator
• Trained a NN on MNIST in Python
• Quantized Weights
• Ran the Verilog prototype in Verilator and checked outputs against the reference

ZedBoard — Booted into Linux

• Flashed the boot image and brought the board up over the UART console
• Filesystem mounted and a static IP (192.168.1.10) configured
• GEM Ethernet up on the Marvell 88E1510 PHY
• telnet / http / ftp / SSH daemons and OLED display started
• Dropped into an interactive shell on the Zynq

UART serial console — Zynq boot log

MNIST Model + Verilator Prototype

• Trained a NN on the MNIST handwritten-digit dataset
• 728 Pixels – 128 Neurons — 10 Neurons
• Simulated the Verilog prototype in Verilator
• Tested on image pixels from MNIST
• Confirms the offline-to-live path: Python NN → System Verilog → simulation

CNN Model for Web Fingerprinting

• Quantized and optimized model from FP32 to Int8
• Combined layers for higher throughput
• Identified causes for loss of accuracy and used findings to modify data pipeline and retaining accuracy.
• Explored and modified architecture design and choices to meet latency goals.
• Tested new INT8 model to meet requirements needed for FPGA multiplication.

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Goals — Week 4

• Deploy the trained model onto the ZedBoard and run inference on-device
• Optimize the design — reduce clock cycles and pipeline the layers
• Measure accuracy and latency of the hardware vs. the Python reference
• Continue developing toward live packet-metadata classification

Thank You!