Reduced Instruction Set Computing

(RISC)

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What you’ll learn

• How CISC and RISC architectures are comparable?

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Central Processing Unit: Introduction, General Register Organization, Stack Organization, Instruction Formats, Addressing Modes, Data Transfer and Manipulation, Program Control, Reduced Instruction Set Computer (RISC)

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CISC and RISC

Before the 1970s: Trend was to construct more complex instruction sets containing hundreds of instructions and variations.

CISC (Complex Instruction Set Computer)

• Designed to simplify compilation.
• Single instruction for each high-level language statement.
• Some of which may only be rarely used in practical programs.
• Around 80% of them used 20% of the time only

RISC (Reduced Instruction Set Computer)

• Simplification by implementing frequently used instructions,
• Less common operations are implemented as subroutines
• Additional execution time is offset by infrequent use

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• Many instructions (∼100 to 250) that implement complex tasks.
• More complex addressing modes (∼5 to 20).
• More complex instructions.
• Programs that tend to be smaller in size
• Some perform specialized tasks and are used infrequently.
• An instruction may span multiple words.
• Variable length instruction formats.
• Instructions to manipulate operands in memory as well as registers.
• Memory transfers using a single MOVE instruction.

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CISC Characteristics

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RISC Characteristics

• Fewer instructions in the instruction set (∼100).
• Simple addressing modes (∼3)
• All instructions fitting in a single word. Fewer instruction formats.
• Single-cycle instruction execution
• A hardwired control unit
• Minimized memory access
• The CPU has a relatively large register set.
• Ideally, most operations can be done register to register.
• Memory access performed by load/store instructions only
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RISC Characteristics contd..

• Pipelined execution
• Fast execution of all instructions by utilizing a large number of parallel data paths and overlapping the fetch and execute phases of successive instructions
• Programs that tend to be larger in size,
• because more, but simpler instructions are needed to perform complex tasks.
• Support for most frequently used operations in the application inherently in the machine design, by using a judicious choice of instructions and optimized compilers

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Performance

Computer performance, as measured by program execution time, is directly proportional to clock cycle time, the number of clock cycles per instruction, and the number of instructions in the program.

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Shortening the clock cycle results in improved performance.

• CISC machines increase performance by reducing the number of instructions per program.
• RISC machines minimize the number of cycles per instruction.

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Performance

At the gate level, both RISC and CISC systems perform an equivalent quantity of work

• CISC machines rely on microcode to tackle instruction complexity.
• In RISC systems, the complexity removed from the instruction set is pushed up a level into the domain of compiler
• RISC designs move the complexity from hardware to software.

Compromise: For example, it is attractive to add some non-RISC instructions to a RISC processor in order to reduce the number of instructions executed, as long as execution of these instructions is fast

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CISC vs RISC

Suppose register-to-register moves, adds, and loop operations each consume one clock cycle and multiplication requires 30 clock cycles to compute the product, 5 x 9:

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Chip Complexity

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RISC design reduces instruction complexity resulting in simpler chips.

• Transistors formerly employed in the execution of CISC instructions are used for pipelines, cache, and registers.

High-level languages depend on modularization for efficiency. Procedure calls and parameter passing

RISC chips having hundreds of registers, the saving and restoring sequence can be reduced to simply changing register environments.

• When a program is executing in one environment, only one register set is visible. If the program changes to a different environment (when procedure is called), the visible set of registers for the new environment changes.

Typically 16 register sets (or windows) of 32 registers each are included

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Register Windowing

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Register windows are a feature which dedicates registers to a subroutine by dynamically aliasing a subset of internal registers to fixed, programmer-visible registers.

• Implemented to improve the performance of a processor by reducing the number of stack operations required for function calls and returns

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Register Windowing

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CWP: Current window pointer

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Register Window Relationships

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• G is the number of global registers,
• L is the number of local registers in each window,
• C is the number of registers common (input and output) to two windows
• W is the number of windows

Then

Window size (number of registers available for each window) is L+2C+G

Register file (total number of registers needed in the processor) is (L+C)W+G

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Recap

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Video Links

• RISC Architecture by Education 4U
• CISC Architecture by Education 4U
• RISC vs CISC by Sudhakar Atchala
• RISC and CISC by Education 4U
• RISC and CISC architecture by Tutorials point
• RISC architecture GATE Exercise by Tutorials point

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