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CXL USE CASES & �MICROARCHITECTURE EXPLORATION

NATHAN KALYANASUNDHARAM

AMD

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| CXL PANEL DISCUSSION – UCSC | NOVEMBER 16, 2022 |

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CACHING HIERARCHY

  • System Goals - lower latency, reduce data movement, lower power, lower cost and improve performance
  • Flash is significantly cheaper but also significantly higher latency, >=5us & <= 50us.
  • Multiple layers of switching adds latency
  • Caches will play a critical role
  • CPU, Switch and Devices may have caches dedicated for CXL memory
  • Problem: �Each product more likely to develop caching policies independently

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  • “Attack of the Killer microseconds” – google paper, still a problem
    • What should CXL do?
    • Can smart caching make the “killer microseconds” extremely rare?
    • Return a wait code and fall back to monitor/mwait to save power

CXL ARRANGEMENT

SCT : system cache tier

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| CXL PANEL DISCUSSION – UCSC | NOVEMBER 16, 2022 |

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CACHING HIERARCHY

  • Research topics to explore
    • Caches are critical to solve endurance and latency issues.
    • How much cache capacity (as a % of memory capacity) is needed in each hierarchy for classic and emerging workloads
    • Mechanisms for the different levels of cache hierarchy to co-operatively solve the problem
    • Cache allocation policies at each level
      • Write back vs write around vs write through
      • Smart allocators – anything beyond the known set dueling/sampling style.
    • At what point it becomes too many levels. Most CPU products have 3 levels of caches. Is two more levels one too many?
    • Should the caches be used only for prefetching data?
  • Software prefetch
    • Current prefetches are defined to pull data into CPU cache.
    • If a new prefetch semantic is available to pull cache line or block into a system cache tier (SCT), which workloads will benefit most?
    • Can the kernel prefetch pages from cold memory before a VM is launched?

RESEARCH TOPICS

SCT : system cache tier

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| CXL PANEL DISCUSSION – UCSC | NOVEMBER 16, 2022 |

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CXL FABRIC USE CASES

Composable Systems

CPU based scale out systems (HPC/Analytics)

Accelerator based scale out systems (ML)

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| CXL PANEL DISCUSSION – UCSC | NOVEMBER 16, 2022 |

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CACHING HIERARCHY

  • Is there value to simplify and only enable software coherency?
    • CXL Fabric to a large extent will rely on software coherency. It is very hard to scale coherency across domains.
  • Develop cache flush widgets to reduce software overhead.
    • Example, tracker and flush filter mechanism to speedup flush, etc.,
  • What sort of new instructions should be included in CPU ISA? Example, a new PGFLUSH (page flush)?
  • Are there any fast synchronization widgets needed?

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CXL FABRIC

SCT : system cache tier

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| CXL PANEL DISCUSSION – UCSC | NOVEMBER 16, 2022 |

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DISCLAIMER & ATTRIBUTION

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ATTRIBUTION

© 2015 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. in the United States and/or other jurisdictions. Other names are for informational purposes only and may be trademarks of their respective owners.

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| CXL PANEL DISCUSSION – UCSC | NOVEMBER 16, 2022 |