Design and Implementation of Different Components of CPU Using Verilog HDL��Ahsanullah University of Science And Technology
Dept of EEE
A Thesis presentation Submitted By
Md Fakrul Islam Javed: 170205172
Tahsina Tashrif Shawmee: 170205152
Mashiyat Marzukah: 170205177
A.N. M. Mahbub Rashed Tarafdar: 160205159
Design and Implementation of Different Components of CPU Using Verilog HDL��Ahsanullah University of Science And Technology
Dept of EEE
A Thesis presentation Submitted By
Tahsina Tashrif Shawmee: 170205152
Contents
1. Our Design Specification (Introduction)
2. Arithmetic Logic Unit (ALU)
3. Register
4. RTL Design
5. Custome Design
6. Placement and Routing
Objective
Propose to design 8 bit-CPU
Implemented ALU, Register and Control unit
Verilog (Modelsim)
Custom design by Cadence-EDA
Physical Design ( PNR)
ALU
8 bit data and 8 Operation
To perform Arithmetic and logical operations
Addition, Subtraction, Increment operations
OR, AND, NAND, NOR and XOR operations
Multiple Precision Arithmetic Operation, Complex Operation
Calculation Pipeline, Iterative Calculation
REGISTER
J-K Flip Flop
8 bit data
6 register
Implemented with 8x1 MUX, 1x8 DEMUX
8 bit data store per block
PIPO Register
CONTROL UNIT
Register Address
10 bit Instruction
ALU operations control
Register control
Read Data 1 Read Data 2
Mux Control
Our Design Specification:
TOOLS
ModelSim Intel FPGA Edition 2020.1
Quartus II 9.0sp1 Web Edition
Cadence Virtuoso
Genus Tool
Gvim, Draw.io, MS Office, Powerpoint
Design and Implementation of Different Components of Processor Using Verilog HDL��Ahsanullah University of Science And Technology
Dept of EEE
A Thesis presentation Submitted By
A.N. M. Mahbub Rashed Tarafdar: 160205159
Register
Collection of binary cells that retains binary data for that collection.
Connects storage cells to the circuits that are required to transmit data in and out of storage.
Four different modes of operation: SISO, SIPO,PISO, PIPO
VERILOG DESIGN OF REGISTER:
Analog Design of Register:
Implementation: 8 bit register block design
Implementation: Resultant waveshape
Key points about the Analog design:
PIPO mode of operation
Used 8 register in single colums and every column has 6 lines
Used 6 pins of 1:8 demux; 2 pins were directly connected to output.
No floating point
No shorted output issues.
Design and Implementation of Different Components of Processor Using Verilog HDL��Ahsanullah University of Science And Technology�Dept of EEE
A Thesis presentation Submitted By
Md Fakrul Islam Javed: 170205172
ALU
Composed with input units, output units, arithmetic logic, control units, etc.
perform bitwise and arithmetic operations on integer values in a single device
ALU RTL DESIGN
OUTPUT WAVESHAPE OF RTL DESIGN
Analog design and Output Waveshape
8Bit_ALU Symbol
Output
Control Unit
Control Unit
PLACEMENT & ROUTING�
Cutoff dimension 40*40
Floor Plan
Connectivity
Geometry
PLACEMENT & ROUTING�
Floor Plan for 35x35
Floor Plan
Connectivity
Geometry
PLACEMENT & ROUTING
Area vs Geometry Violation
Area
Geometry Violation
Area vs Occupancy
Area
Occupancy
90
75
60
35
45
40*40
80*80
50*50
60*60
100*100
917
432
265
30*30
35*35
40*40
Design and Implementation of Different Components of Processor Using Verilog HDL��Ahsanullah University of Science And Technology
Dept of EEE
A Thesis presentation Submitted By
Mashiyat Marzukah Prottasha: 170205177
Click to add text
Final RTL Design and output waveshape
Achievement
From 8 bit ALU:
Zero error Verilog implementation and schematic
complex calculation result.
Proper resultant waveshape
From Register:
Custom Register Design
Simple Design.
From Control Unit:
Control all the blocks
Limitations:
COULD NOT COMPLETE THE CPU DESIGN DUE TO TIME LIMITATION.
MEMORY DESIGN
MULTIPLICATION OPERATION
ZERO FLAG AND CARRY FLAG
GLOBAL NET DECLARING
Impacts
Social Implementation
Available for everyone
Reliable
Ethical
No copyright issue
Cost
Less expensive
THANK YOU
ANY QUESTIONS?