EE 198: EECS151 Tapeout

Lecture 1: What is this all about?

University of California, Berkeley

IEEE Student Branch

University of California, Berkeley

IEEE Student Branch

Introduction

All you need to pretend you read the syllabus.

• Welcome!
• Course Staff Introduction
• All Kinds of Logistics
• Welcome to BWRC! (What is BWRC?)
• Jumping right in.. What even is this “tapeout” I signed up for?
• Crash course review of EECS151
• VLSI and Hammer
• Self-introductions and discussion

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Welcome!

You are now part of the EECS151T v3! Fall 2025

• Brought to you by:
• The IEEE Student Branch at UC Berkeley
• Check out @ https://ieee.berkeley.edu/join !
• Berkeley Wireless Research Lab
• Check it out @ https://bwrc.eecs.berkeley.edu/ !
• Advisor: Borivoje (Bora) Nikolic
• The US Government (NSF, CHIPS Act.. etc.)
• You! :)

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IEEE: How you can join! (Quick ad)

• General member sign-up: berkie.ee/gm-app
• No essays, no interviews, all are welcome!
• Rolling Admissions
• Committee Officer Applications
• Can be found in the infosession slides here ->

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What is a “tapeout”?

• From software to custom silicon (but with a *few* extra steps…)

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What is a “tapeout”?

• From software to custom silicon (but with a *few* extra steps…)

​

Software

Silicon

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But why do a tapeout / “custom silicon”?

EECS151LB Enthusiast: “Why not just use an FPGA?” Great question!

9k logic cells.. DDR and PCIE.. what else could I possibly need in life?..

25$ or 20k$?

hmmmmmm

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Beyond the cost vs PPA argument for ASICs

• In EECS151, the common conclusion is that FPGAs are cheaper but ASICs are better for power, performance, and area
• However, there is also a purpose argument
• FPGAs are still useful for computer architecture / system studies
• However, they make difficult experiments at lower abstractions
• Circuits, interconnects, devices - things EECS151 labs hide
• But we’ll see are still important for the physical design of a digital system

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Beyond the cost vs PPA argument for ASICs

“An ASIC is circuit design - on an FPGA, you configure somebody else’s circuit. It boils down to - does your experiment require circuit design?”

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Use Case -> Requirements -> Experiment Design -> Implementation

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Never forget these first steps

• In this class, the main One Fifty One (OFO) Tile project might not alone be the most revolutionary SoC in the world.. >_>
• Though you can work on side projects if you progress quickly!
• But keep in mind the motivation
• + what you can create with this unique opportunity!
• What kinds of questions might a tapeout help you answer?
• “Great, I wrote a spec for this digital protocol. We’re basically done, right?”
• “Why can’t my design just use more memory? I’ll make it external!”
• “I’m doing digital input/output (IO) on the SoC, why do I care what a level shifter is, isn’t that just the PCB designer’s problem?”

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You’re not alone - tapeouts are on the rise!

• Undergraduate tapeouts are increasing across the country
• Some even student-run (clubs, project teams..)! But still very few..
• Barriers are falling (open source processes/tooling, democratization..)
• Start-up and educational tapeouts more common
• Ex: TinyTapeout (100-300$ mini-tapeout)
• Berkeley has an impressive Tapeout course + research infrastructure
• While interest climbs, the barrier is still high

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So why join the EECS151T Tapeout Decal?

• With the EECS151T Decal, we aim to:
• Reduce barriers to entry to VLSI + SoC design for diverse demographics
• Particularly bridge between EECS151 -> EE194 Tapeout
• Invigorate interest in VLSI research + open source community
• Facilitate more holistic end-to-end system learning
• Not as “block” focused as EE194 Tapeout
• Build a student-run tapeout community
• Empowering (sorry) us to build silicon on our own terms
• And choose our applications
• Ex: Stanford partnering with biotech labs

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So why join the EECS151T Tapeout Decal?

• With the EECS151T Decal, we aim to:
• Etc etc, big words..
• It’ll be FUN :)

(our)

ASIC

you

me

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Course Staff!

Etc, Ask Us Anything! (in a bit..)

Loren Hung

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Connor Lu

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Borivoje (Bora) Nikolic

Decal Advisor

Very Cool EECS Professor

BWRC & SLICE Labs

Borivoje Nikolic | EECS at UC Berkeley

Jim Fang

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Nathan Carter

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Justin Yang

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Marie-Anne Xu

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Ian McLellan

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A few words from Prof. Shao!

Sophia Shao

Decal Advisor

Very Cool EECS Professor

BWRC & SLICE Labs

Sophia Shao | EECS at UC Berkeley

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EECS151/251A ASIC Labs

In Fall’23 migrated to SkyWater 130nm technology

• Not much different than the TI 180nm process
• Labs get us a few steps away from actual chip tapeouts
• Designs done in SkyWater 130nm

(some more pipecleaning is helpful)

Funding for chips: �Microelectronics Commons NW AI Hub

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The Syllabus

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Logistics

• EE 198-020 - Enrollment codes given out today!
• 2 Unit P/NP (6 hours / week)
• Average 4(+) hours outside of class for project work
• More project work toward the latter half of the course
• Class time: Fridays 3-4:30pm, BWRC
• Office hours & Work sessions (add it to your gCal): https://151tapeout.berkie.ee/calendar/
• Website: https://151tapeout.berkie.ee

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Logistics

• Most up to date links, if not on website, will be on Discord
• Join the Gradescope
• add code: Entry Code - NGJYBG
• https://www.gradescope.com/courses/1094924
• Lab manual & repos on Github
• https://github.com/ucb-eecs151tapeout/eecs151t-labs
• We will ask for your GitHub usernames

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Logistics - The Official Grading Rubric

• Your grade is primarily based on progress towards project milestones. The final results are graded on effort and a demonstration of concepts taught in the course.
• Students need 70% to pass.

40% - Gradescope lab submissions.

40% - midterm & final presentations and documentation.

20% - participation (through attendance or check-ins).

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Logistics

• DSP requests and special accommodations: email us!
• Late assignments and extensions: email us!
• Will be decided on a case-by-case basis
• Deadlines are meant to motivate, not punish
• Most announcements, discussion, door access will be Discord
• Join Discord link: berkie.ee/151t-discord
• Questions? Ask now!
• Or email us! 151tapeout@ieee.berkeley.edu

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Checkout the website for timeline!

Disclaimer: things never go as planned in life :)

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Part One:

Frontend (RTL)

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Checkout the website for timeline!

• starting side projects (optional)

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Part Two:

Verification

*deadlines flexible

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Checkout the website for timeline!

Note: the tapeout deadline is EARLY (we only get 9 group meetings!)

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Part Three:

Back-end (PD)

*deadlines flexible

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What does it mean to be a very new Decal?

• While the lofty goal is reasonably achievable..
• The “course” is not 100% complete yet
• We purposefully made this a small cohort
• We want your feedback on lectures + labs!
• Both if you have + don’t have background
• If things break, let’s work together to fix them!
• Feel free to add your own spin on things!
• Grades (P/NP) are mostly effort based
• But don’t ghost.. >:l

(our)

ASIC

you

me

(not a cliff)

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Questions?

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Welcome to BWRC:

The Berkeley Wireless Research Center!

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What is the BWRC?

• Not a regular “classroom”.. a research lab full of PhD students & professors who won’t appreciate being disturbed too much!

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What is the BWRC?

• We are privileged to be here!
• Respect is important
• (For now) Decal students do not use the Main Labs
• Or go into photonics area
• Or steal kitchen snacks..
• We will not be running anything on BWRC compute
• Use EECS instructional machines

Entrance

Main Labs

Brian

Lecture Hall

Rabey

Photonics

Jeff

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BWRC Rules

• No keycard access - ping in the Discord instead
• Do not touch other people’s stuff, including interesting electronics and snacks
• Using the kitchen for water is okay
• BWRC folks have access to a lot of NDA / secret materials..
• The Decal will interface with these minimally, but keep in mind lab warnings NOT to post certain things on public repositories
• We won’t talk about CAD/Gitlab/LSF/etc rules since not Decal-relevant

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EECS Instructional Machines

• We will be using EECS Cory compute, similarly to EECS151 Labs
• Lab 1 will guide you through the setup
• https://acropolis.cs.berkeley.edu/~account/webacct/

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Questions?

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What is VLSI?

EECS151 Crash Course Review

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VLSI Background

• What is “VLSI” (Very Large Scale Integration)?

​

Thanks Wikipedia!

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VLSI Background

• In reality, already an outdated term
• People tried “ULSI” (“Ultra” Large) and gave up naming things..
• But everyone* still talks about - and hires for - the VLSI stack

..maybe more than ever!

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Bonus meme for those who read the slides

*Not really true... still funny.

*

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Okay, but what is the VLSI stack really?

• “To succeed in the VLSI design flow process, one must have a robust and silicon-proven flow, a good understanding of the chip specifications and constraints, and absolute mastery over the required EDA tools (and their reports).” -

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Synthesis

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But wait.. You’re already familiar with this!

Remember your

EECS151 Labs!

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EECS151LA Labs In One Slide (FA23)

• Lab 1: VLSI Compute Environment Setup
• i.e. the “Forget the GUI” Lab: Unix, Makefiles..
• Lab 2: RTL vs Gate-Level Simulation
• Lab 3: Logic Synthesis
• Lab 4: Physical Design
• Place-and-Route (PAR): Floorplan, clock tree..
• Lab 5: Physical Design
• The “Route” part of PAR..
• Lab 6: (Mini…) Integration

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(Weeks of labor in small bullet points….. )

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EECS151LA Labs In Multiple Slides

• Let’s break down the abstraction a bit

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(Note: this was taught a bit differently depending on semester + FPGA vs ASIC labs..)

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(STEP 0) VLSI Review: Using Linux

• EECS151 Labs introduced you to VLSI environments

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• Basics like: CLI commands, Regex, vim, Makefiles, vim, dotfiles, tmux..
• If you need review, revisit to your EECS151 lab doc!
• Environment setup in this Decal will also take some effort, but will get easier over time!

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https://github.com/EECS150/asic-labs-sp24/tree/main/lab1

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(STEP 1) Spec, Architecture, and RTL Design

• EECS151 Taught you to fear and love the classic RISC-V 5 ( or 3..)-stage pipelined CPU
• You were probably exposed to caches.. maybe SRAMs and accelerators, depending on semester / class

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(STEP 1) Spec, Architecture, and RTL Design

• You spent a lot of your time doing microarchitecture..
• With RTL design confined to Verilog
• But what’s the bigger picture?
• We’ll find out!

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Architectural Block Diagrams

• Assuming your VLSI specifications are completed and approved by the different parties, it’s time to start thinking about the architectural design.
• In VLSI system design phase, the entire chip functionality is broken down into small pieces with a clear understanding of the block implementation.
• For example: for an encryption block, do you use a CPU or a state machine.
• Some other large blocks need to be divided into subsystems and the relationship between the various blocks has to be defined.
• In this phase the working environment is documentation.

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https://anysilicon.com/vlsi-design-flow-overview/

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RTL (Register Transfer Level)

• For digital VLSIs or for digital blocks within a mixed-signal chip, this phase is basically the detailed logic implementation of the entire VLSI.
• This is where the detailed system specifications is converted into VHDL or Verilog language.
• In addition to the digital implementation, functional verification is performed to ensure the RTL design is done according to the specifications.

https://anysilicon.com/vlsi-design-flow-overview/

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(STEP 2 … and onwards) Simulation

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• You did RTL (behavioral) and gate-level simulations

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• Review Lab 2 if you need to:
• CAD Tools (emphasis on VCS and DVE)
• Hammer
• Skywater 130mm PDK
• Behavorial RTL Simulation
• Gate Level Simulation
• Simple Power Analysis

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(STEP 2) RTL Simulation

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• You did RTL (behavioral) and gate-level simulations

​

• Review Lab 2 if you need to:
• CAD Tools (emphasis on VCS and DVE)
• Hammer
• Skywater 130mm PDK
• Behavorial RTL Simulation
• Gate Level Simulation
• Simple Power Analysis

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What are these, really?

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(STEP 3) Logic Synthesis (Throwback to Lab 3)

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• When all the blocks are implemented and verified the hardware description (RTL) is converted to a gate-level netlist
• by a synthesis tool that takes in a standard cell library, constraints, and the RTL code to produce a netlist
• Synthesis tools run different algorithm implementations to provide the best netlist that meets these constraints
• What constraints? Power, speed, size, timing margins…
• Results can vary!

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(STEP 4) Gate Level Simulation

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• Little for a CPU.. but when PAR takes days, you don’t want to rerun often!

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(STEP 5) Place and Route & Physical Layout

• Gate-level netlist -> to complete geometric representation
• Floorplanning (Initial Layout)
• Hierarchical block placement
• I/O Pads (what are those?!)
• Power Planning
• Power rails?!
• Design Placement
• Elements within each block
• Analog blocks & external IP

Data Preparation

Time Design

Floorplanning

Power Planning

Place Design

Routing

DRC/LVS

Signal Integrity

(Throwback to lab 4)

CTS (Clock Tree Synthesis)

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(STEP 5) Place and Route & Physical Layout

• Clock Planning
• Where’s the clock coming from, anyway?...
• Routing
• Metal layers?? Is this a PCB??
• When all the elements are placed, global + detailed routing connects all
• ..all iterating over and over to analyze + optimize!

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Data Preparation

Time Design

Floorplanning

Power Planning

Place Design

CTS (Clock Tree Synthesis)

Routing

DRC/LVS

Signal Integrity

(Lab 5 Throwback)

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(STEP 6) More simulation! (DRC)

• ​
• Who *actually* did that part?
• Makefile magic
• “Layout” -> lithography mask..
• Design Rule Checking (DRC)
• Foundries aren’t perfect..
• What rules help them manufacture your mask?

Data Preparation

Time Design

Floorplanning

Power Planning

Place Design

CTS (Clock Tree Synthesis)

Routing

DRC/LVS

Signal Integrity

(Lab 6 Throwback ish)

​

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(STEP 7) More simulation! (LVS)

• ​
• Who *actually* did that part?
• Makefile magic
• “Layout” -> lithography mask..
• Layout vs Schematic (LVS)
• DRC says nothing about intended functionality
• Does the layout correspond to the circuit you wanted?

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Data Preparation

Time Design

Floorplanning

Power Planning

Place Design

CTS (Clock Tree Synthesis)

Routing

DRC/LVS

Signal Integrity

(Lab 6 Throwback ish)

​

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(STEP 8) Tapeout!

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• GDSII creation
• The file produced at the output of the layout is the GDSII (GDS2) file
• i.e. the file used by the foundry to fabricate the silicon

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(STEP 8) Tapeout!

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• GDSII creation
• The file produced at the output of the layout is the GDSII (GDS2) file
• i.e. the file used by the foundry to fabricate the silicon

​

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….Abstraction, save us!

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A decent review? Or new stuff?..

• Lab 1: VLSI Compute Environment Setup
• i.e. the “Forget the GUI” Lab: Unix, Makefiles..
• Lab 2: RTL vs Gate-Level Simulation
• Lab 3: Logic Synthesis
• Lab 4: Physical Design
• Place-and-Route (PAR): Floorplan, clock tree..
• Lab 5: Physical Design
• The “Route” part of PAR..
• Lab 6: (Mini…) Integration

​

(Weeks of labor in small bullet points….. )

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Which way..?

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“Honestly I think learning the EDA tools is kinda the easy part. You read the manuals, pick up a few tricks from more senior colleagues, etc. The path to understanding is more or less straightforward and obvious. Which is not to say one won’t spend a ton of frustrating hours on it. One definitely will. But the learning path itself is understood. And if you grind through it, you’ll get to the other side.” - Very Cool Engineer Eric

“RTL design flow is one of the most successful software flows in human history” - Very Cool Professor Alberto

We’ll see what you think after getting more acquainted with these!

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Questions?

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What is missing from the picture?

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From CPU to (System-on-Chip) SoC

• A lot of VLSI steps are simplified in EECS151LA because the CPU is a relatively small module (/ core)
• What happens when you add it to a whole system?
• Maybe we can call it a system on chip?

Core0

Peripherals

(JTAG, UART..)

Scratchpad, SRAMs..

(Not just your CPU caches)

PLL (clock modules)

Etc etc etc

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What if we don’t reinvent the wheel SoC?

• Generations of engineers have generated vast amounts of IP
• IP -> Intellectual Property -> analog and digital modules, tools etc..
• What if we don’t buy expensive proprietary IP?
• A lot of hardware / silicon IP is open-source already

A very “not cheap” SoC..

instant noodle budget..

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Hence - Chipyard!

• We will talk more about existing IP, how it combines to form an SoC, and how to use the generator features of Chipyard
• Particularly using a language called Chisel (instead of Verilog)
• In use by much Berkeley VLSI research + many in industry

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Wait, is that Hammer? Yes!

• Some EECS151LA iterations explicitly brought up Hammer flows
• But even if you don’t know about it, you were probably using them
• We will delve into them into much more detail!
• We have to sim + verify the whole SoC
• When taping out, DRC/LVS is not “optional”.. :(

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(EECS151LA Lab 2)

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Another Possible Throwback: SKY130

• You might’ve also talked about the SKY130 PDK
• In EECS151LA, the mystical foundry is the least of your worries
• In this Decal, the choice of PDK becomes very important!
• Particularly when it comes to limitations (Ex: SRAMs..)

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And many, many other things go into SoCs

Validation? DFT? Bring-up? Booting an SoC?

This is y/our tapeout, let us know what you’re interested in!

Etc Etc Etc

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Oh hey.. That’s the class description

Now you know what we’re talking about!

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Questions?

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Introduction (Summary)

All you need to pretend you read the syllabus.

• Welcome!
• Course Staff Introduction
• All Kinds of Logistics
• Welcome to BWRC! (What is BWRC?)
• Jumping right in.. What even is this “tapeout” I signed up for?
• Crash course review of EECS151
• VLSI and Hammer
• Self-introductions and discussion

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The upcoming weeks..

• Everything is very new - please give feedback!
• We will have lectures with more theory - you don’t have to listen
• The labs are practical guides using the OFOT Project
• And you will have a chance to work on your own side project!

Everything will be communicated through Discord.

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Actionables

• If most of this intro was a review, you’re in great shape!
• Review the 151 Labs if you need, there’s a lot of good info in those READMEs!
• Get enrollment code! Give us your Github username!
• Let’s get everyone on Gradescope!
• And on the Github:
• Prelab 1: Git
• Lab 1a: Chipyard Setup
• Lab 1b: Chisel Bootcamp
• Try to get past 1a by lecture 2!

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(dates diff -_-)

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Also next time: Self-Introduction Slides

(we’re a small class, let’s get to know each other!)

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Ex:

Name + ~5 pictures of something relevant to you

Anything you may want us to know (pronouns/hometown/hobbies?)

Why you want to do a tapeout?

Pitch us a side project if you’d like!

We will send out a deck on discord

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Questions?

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Let’s tape this chip out!*

*soon (™)

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Permission Code Distribution™

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