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CORE-V Cores Naming Conventions

October 2021

Davide Schiavone	davideⓐopenhwgroup.org

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CORE-V Part Numbers (P/Ns)

October 2021

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Current CORE-V Cores P/N Syntax

October 2021

CV32E40P

FAMILY

CORE-V

word-length

CLASS

Embedded, Application

IDENTITY

pipe length, specific feature

MODIFIER

special cases

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Proposed CORE-V Cores P/N Syntax

October 2021

CV32E40P

[ Identity ]

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CORE-V Cores P/N Semantics

October 2021

Family	Word Length	Class	Pipeline length	Identity�-Specific Feature-	Identity�-Modifier-
CORE-V (CV)	32, 64	Embedded Application Server	Pipeline Length usually defines the most important computer architecture feature	Same pipeline length core can have different ISA, order of execution, other microarchitectural changes (fast divider, interrupts, debug, etc)	Extra identifier to make the core unique and easily identifiable within the same family (as the first name for humans)

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CORE-V Cores Repository Name

Once the Semantic of the CORE-V IP is defined, there is a unique RTL repository hosted in Github named according to the P/N

November 2021

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CORE-V Project Name

Each CORE-V Project can target one or more CORE-V IPs.

The output of the Project related to a specific CORE-V IP produces at PF time a unique identifier called:

P/N_vMAJOR.MINOR.PATCH

e.g. Project CV32E40P_v1.0.0 achieved on Dec 2020

e.g. Project CV32E40P_v2.0.0 will be achieved on Dec 2022

e.g. Project CV32E41P_v1.0.0 will be achieved on Dec 2021

November 2021

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CORE-V IP Maintenance

Everytime a project achieves PF, a Github tag with the Project name must be created to identify the project outcome

Unless bugs are found or a following project aims to complete a previous project, subsequent changes in the RTL must be Logical Equivalent to the core

If bugs are found, a new project to address the bug must be defined

Project names must also be reported in the RTL in the RISC-V mimpid register

November 2021

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CORE-V IP Identification

Software refers to a specific CORE-V IP my using the following 3 registers

marchid are maintained here: https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md

mvendorid are asked to RISC-V/JeDEC

November 2021

mvendorid	Identifies OpenhW Group
marchid	Identifies the P/N
mimpid	Identifies the Project

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Examples

Creation of the CV32E40P IP

CORE-V, 32bits, Embedded, 4 pipe stages, 0 to refers to its ISA, in-order, microarchitecture, �P to remind PULP
mvendorid → 0x0000_0602 to refer to as OpenHW Group
marchid → 0x0000_0004 to refer to CV32E40P

Project v1 to verify the RV32IMC ISA subset

Github Tag CV32E40P_v1.0.0 achieved on Dec 2020 at PF time
mimpid → 0x0000_0000
if changes in the RTL happens outside the project, they must be LEC to the latest project outcome

Project v2 to verify the RV32FXPULP ISA subset

Github Tag CV32E40P_v2.0.0 will be achieved on Dec 2022 at PF time
mimpid → 0x0000_0001
if changes in the RTL happens after the project (e.g. doc) , they must be LEC to the latest project outcome

Project v2 maintained to solve a bug in found in the float divider when debug and interrupts arrive together

Github Tag CV32E40P_v2.1.0 will be achieved on March 2025 at PF time
mimpid → 0x0000_0002
if changes in the RTL happens after the project (e.g. doc) , they must be LEC to the latest project outcome

November 2021

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Examples

Creation of the CV32E41P IP

CORE-V, 32bits, Embedded, 4 pipe stages, 1 to refers to its ISA, in-order, microarchitecture, �P to remind PULP
mvendorid → 0x0000_0602 to refer to as OpenHW Group
marchid → 0x0000_001B to refer to CV32E41P

Project v1 to verify the RV32ZfinxZce ISA subset

Github Tag CV32E41P_v1.0.0 achieved on Dec 2021 at PF time
mimpid → 0x0000_0000
No LEC restriction if not TRL5

Creation of the CV32E41 IP

CORE-V, 32bits, Embedded, 4 pipe stages, 1 to refers to its ISA, in-order, microarchitecture, removed PULP extensions
mvendorid → 0x0000_0602 to refer to as OpenHW Group
marchid → 0x0000_001C to refer to CV32E41

November 2021

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and

OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where HW and SW designers collaborate in the development of open-source cores, related IP, tools and SW such as the CORE-V Family of open-source RISC-V cores

OpenHW Group & CORE-V Family of open-source RISC-V cores for use in high volume production SoCs

Visit the OpenHW CORE-V Cores GitHub repository and contribute
Learn more at OpenHW TV

October 2021