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RISC-V Processor Design�Control

CS61C

UC Berkeley�Teaching Professor �Dan Garcia

cs61c.org

Great Ideas

in�Computer Architecture

(a.k.a. Machine Structures)

Garcia, Kao

21-Control (1)

Garcia, FA25

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Datapath Control

21-Control (2)

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Review

We have designed a complete datapath

Capable of executing all RISC-V instructions in one cycle each
Not all units (hardware) used by all instructions

5 Phases of execution

IF, ID, EX, MEM, WB
Not all instructions are active in all phases

Controller specifies how to execute instructions

We still need to design it

21-Control (3)

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Our Single-Core Processor

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Single-Cycle RV32I Datapath and Control

+4

Add

clk

addr

inst

IMEM

addr

DMEM

PC

pc+4

Inst[24:20]

ALU

clk

Reg [ ]

Inst[19:15]

Inst[11:7]

AddrB

AddrA

DataA

DataB

AddrD

DataD

alu

R[rs1]

R[rs2]

Control logic

0

1

Bsel

Imm.

Gen

Inst�[31:20]

ImmSel�

DataB

WBSel

0

1

MemRW

clk

0

1

Branch

Comp

mem

0

1

pc

PCSel

BrUn

BrEq

BrLT

Asel

2

Inst[31:0]

Imm[31:0]

RegWEn

ALUSel

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Example: sw reg, offset(regbaseptr)

ALUSel

+4

Add

clk

addr

inst

IMEM

addr

DMEM

PC

pc+4

Inst[24:20]

ALU

clk

Reg [ ]

Inst[19:15]

Inst[11:7]

AddrB

AddrA

DataA

DataB

AddrD

DataD

alu

R[rs1]

R[rs2]

Inst[31:0]

Control logic

RegWEn

0

1

Imm[31:0]

Bsel

Imm.

Gen

Inst�[31:20]

ImmSel�

DataB

WBSel

0

1

MemRW

clk

0

1

Branch

Comp

mem

0

1

pc

PCSel

BrUn

BrEq

BrLT

Asel

2

=pc+4

=S

=0

=*

=1

=0

=add

=Write

=*

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Example: beq reg1, reg2, Label

ALUSel

+4

Add

clk

addr

inst

IMEM

addr

DMEM

PC

pc+4

Inst[24:20]

ALU

clk

Reg [ ]

Inst[19:15]

Inst[11:7]

AddrB

AddrA

DataA

DataB

AddrD

DataD

alu

R[rs1]

R[rs2]

Inst[31:0]

Control logic

RegWEn

0

1

Imm[31:0]

Bsel

Imm.

Gen

Inst�[31:20]

ImmSel�

DataB

WBSel

0

1

MemRW

clk

0

1

Branch

Comp

mem

0

1

pc

PCSel

BrUn

BrEq

BrLT

Asel

2

=B

=0

=*

=1

=add

=Read

=*

21-Control (7)

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Instruction Timing

21-Control (8)

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Example: add rd, reg1, reg2

ALUSel

+4

Add

clk

addr

inst

IMEM

addr

DMEM

PC

pc+4

Inst[24:20]

ALU

clk

Reg [ ]

Inst[19:15]

Inst[11:7]

AddrB

AddrA

DataA

DataB

AddrD

DataD

alu

R[rs1]

R[rs2]

Inst[31:0]

Control logic

RegWEn

0

1

Imm[31:0]

Bsel

Imm.

Gen

Inst�[31:20]

ImmSel�

DataB

WBSel

0

1

MemRW

clk

0

1

Branch

Comp

mem

0

1

pc

PCSel

BrUn

BrEq

BrLT

Asel

2

=pc+4

=*

=1

=*

=0

=add

=Read

=1

21-Control (9)

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add Execution��e.g.,�add x1,x2,x3

ALUSel

+4

Add

clk

addr

inst

IMEM

addr

DMEM

PC

pc+4

Inst[24:20]

ALU

clk

Reg [ ]

Inst[19:15]

Inst[11:7]

AddrB

AddrA

DataA

DataB

AddrD

DataD

alu

R[rs1]

R[rs2]

Inst[31:0]

Control logic

RegWEn

0

1

Imm[31:0]

Bsel

Imm.

Gen

Inst�[31:20]

ImmSel�

DataB

WBSel

0

1

MemRW

clk

0

1

Branch

Comp

mem

0

1

pc

PCSel

BrUn

BrEq

BrLT

Asel

2

1000

1004

PC

1004

1008

PC+4

add x1,x2,x3

add x6,x7,x9

inst[31:0]

Clock

Reg[2]

Reg[7]

Reg[rs1]

Reg[2]+Reg[3]

alu

Reg[7]+Reg[9]

Reg[3]

Reg[9]

Reg[rs2]

???

Reg[1]

Reg[2]+Reg[3]

wb

Reg[7]+Reg[9]

add control

Control logic

21-Control (10)

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Example: add timing

ALUSel

+4

Add

clk

addr

inst

IMEM

addr

DMEM

PC

pc+4

Inst[24:20]

ALU

clk

Reg [ ]

Inst[19:15]

Inst[11:7]

AddrB

AddrA

DataA

DataB

AddrD

DataD

alu

R[rs1]

R[rs2]

Inst[31:0]

Control logic

RegWEn

0

1

Imm[31:0]

Bsel

Imm.

Gen

Inst�[31:20]

ImmSel�

DataB

WBSel

0

1

MemRW

clk

0

1

Branch

Comp

mem

0

1

pc

PCSel

BrUn

BrEq

BrLT

Asel

2

=pc+4

=*

=1

=*

=0

=add

=Read

=1

Critical path = t_clk-q +max { t_Add+t_mux, t_IMEM+t_Reg+t_mux+t_ALU+t_mux} + t_setup

= t_clk-q + t_IMEM+t_Reg+t_mux+t_ALU+t_mux+t_setup

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Example: lw reg, offset(regbaseptr)

ALUSel

+4

Add

clk

addr

inst

IMEM

addr

DMEM

PC

pc+4

Inst[24:20]

ALU

clk

Reg [ ]

Inst[19:15]

Inst[11:7]

AddrB

AddrA

DataA

DataB

AddrD

DataD

alu

R[rs1]

R[rs2]

Inst[31:0]

Control logic

RegWEn

0

1

Imm[31:0]

Bsel

Imm.

Gen

Inst�[31:20]

ImmSel�

DataB

WBSel

0

1

MemRW

clk

0

1

Branch

Comp

mem

0

1

pc

PCSel

BrUn

BrEq

BrLT

Asel

2

=I

=1

=*

=1

=0

=add

=Read

=0

=*

=pc+4

Critical path = t_clk-q +max { t_Add+t_mux, t_IMEM+t_Imm+t_mux+t_ALU+t_DMEM+t_mux_,

t_IMEM+t_Reg+t_mux+t_ALU+t_DMEM+t_mux}+t_setup

21-Control (12)

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Instruction Timing

IF	ID	EX	MEM	WB	Total
I-MEM	Reg Read	ALU	D-MEM	Reg W
200 ps	100 ps	200 ps	200 ps	100 ps	800 ps

PC

clock

Instr. fetch

Instr. decode

Execute

Memory Access

pc

pc+4

old

instruction

register out

ALU result

memory data

t_IF

t_ID

t_EX

t_MEM

t_WB

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Instruction Timing

Maximum clock frequency

f_max = 1/800ps = 1.25 GHz

Most blocks idle most of the time

E.g. f_max,ALU = 1/200ps = 5 GHz!

Instr	IF = 200ps	ID = 100ps	ALU = 200ps	MEM=200ps	WB = 100ps	Total
add	X	X	X		X	600ps
beq	X	X	X			500ps
jal	X	X	X			500ps
lw	X	X	X	X	X	800ps
sw	X	X	X	X		700ps

21-Control (14)

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Control Logic Design

21-Control (15)

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Control Logic Truth Table

Inst[31:0]	BrEq	BrLT	PCSel	ImmSel	BrUn	ASel	BSel	ALUSel	MemRW	RegWEn	WBSel
add	*	*	+4	*	*	Reg	Reg	Add	Read	1	ALU
sub	*	*	+4	*	*	Reg	Reg	Sub	Read	1	ALU
(R-R Op)	*	*	+4	*	*	Reg	Reg	(Op)	Read	1	ALU
addi	*	*	+4	I	*	Reg	Imm	Add	Read	1	ALU
lw	*	*	+4	I	*	Reg	Imm	Add	Read	1	Mem
sw	*	*	+4	S	*	Reg	Imm	Add	Write	0	*
beq	0	*	+4	B	*	PC	Imm	Add	Read	0	*
beq	1	*	ALU	B	*	PC	Imm	Add	Read	0	*
bne	0	*	ALU	B	*	PC	Imm	Add	Read	0	*
bne	1	*	+4	B	*	PC	Imm	Add	Read	0	*
blt	*	1	ALU	B	0	PC	Imm	Add	Read	0	*
bltu	*	1	ALU	B	1	PC	Imm	Add	Read	0	*
jalr	*	*	ALU	I	*	Reg	Imm	Add	Read	1	PC+4
jal	*	*	ALU	J	*	PC	Imm	Add	Read	1	PC+4
auipc	*	*	+4	U	*	PC	Imm	Add	Read	1	ALU

21-Control (16)

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Control Realization Options

ROM

“Read-Only Memory”
Regular structure
Can be easily reprogrammed

fix errors
add instructions

Popular when designing control logic manually

Combinatorial Logic

Today, chip designers use logic synthesis tools to convert truth tables to networks of gates

21-Control (17)

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RV32I, A Nine-Bit ISA!

Instruction type encoded using only 9 bits:
inst[30], inst[14:12], inst[6:2]

inst[6:2]

inst[14:12]

inst[30]

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Combinational Logic Control

Simplest example: BrUn

inst[14:12]

inst[6:2]

How to decode whether BrUn is 1?

BrUn = inst[13] ∙ Branch

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ROM-based Control

ROM

Inst[30,14:12,6:2]

BrEq

9

PCSel

ALUSel[3:0]

4

11-bit address (inputs)

BrLT

ImmSel[2:0]

3

BrUn

ASel

BSel

MemRW

RegWEn

WBSel[1:0]

2

15 data bits (outputs)

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ROM Controller Implementation

Control Word for add
Control Word for sub
Control Word for or
.
.
.

Address Decoder

.

Inst[]

BrEQ

BrLT

Controller output (PCSel, ImmSel, …)

add

sub

or

jal

11

AND

OR

21-Control (21)

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Control Logic to Decode add

add = i[30]•i[14]•i[13]•i[12]•R-type

inst[6:2]

inst[14:12]

inst[30]

R-type = i[6]•i[5]•i[4]•i[3]•i[2]•RV32I

RV32I = i[1]•i[0]

21-Control (22)

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“And In Conclusion…”

(drum roll)

21-Control (23)

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Call home, we’ve made HW/SW contact!

High Level Language�Program (e.g., C)

Assembly Language �Program (e.g., RISC-V)

Machine Language Program (RISC-V)

Compiler

Assembler

Hardware Architecture Description�(e.g., block diagrams)

Logic Circuit Description�(Circuit Schematic Diagrams)

Architecture Implementation

temp = v[k];

v[k] = v[k+1];

v[k+1] = temp;

lw x3, 0(x10)

lw x4, 4(x10)

sw x4, 0(x10)

sw x3, 4(x10)

1000 1101 1110 0010 0000 0000 0000 0000

1000 1110 0001 0000 0000 0000 0000 0100

1010 1110 0001 0010 0000 0000 0000 0000

1010 1101 1110 0010 0000 0000 0000 0100

IMEM

ALU

Imm

.

Gen

+4

DMEM

Branch

Comp.

Reg

[]

AddrA

AddrB

DataA

AddrD

DataB

DataD

Addr

DataW

DataR

1

0

1

2

1

0

pc

0

1

inst

[11:7]

inst

[19:15]

inst

[24:20]

inst

[31:7]

pc+4

alu

mem

wb

alu

pc+4

Reg

[rs1]

pc

imm

[31:0]

Reg

[rs2]

wb

21-Control (24)

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21-Control (25)

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“And In conclusion…”

We have built a processor!

Capable of executing all RISC-V instructions in one cycle each
Not all units (hardware) used by all instructions
Critical path changes

5 Phases of execution

IF, ID, EX, MEM, WB
Not all instructions are active in all phases

Controller specifies how to execute instructions

Implemented as ROM or logic

21-Control (26)

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Control �and Status Registers

21-Control (27)

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Complete Single-Cycle RV32I Datapath!

ALUSel

+4

Add

clk

addr

inst

IMEM

addr

DMEM

PC

pc+4

Inst[24:20]

ALU

clk

Reg [ ]

Inst[19:15]

Inst[11:7]

AddrB

AddrA

DataA

DataB

AddrD

DataD

alu

R[rs1]

R[rs2]

Inst[31:0]

Control logic

RegWEn

0

1

Imm[31:0]

Bsel

Imm.

Gen

Inst�[31:20]

ImmSel�

DataB

WBSel

0

1

MemRW

clk

0

1

Branch

Comp

mem

0

1

pc

PCSel

BrUn

BrEq

BrLT

Asel

2

21-Control (28)

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Control and Status Registers

Control and status registers (CSRs) are separate from the register file (x0-x31)

Used for monitoring the status and performance
There can be up to 4096 CSRs

Not in the base ISA, but almost mandatory in every implementation

ISA is modular
Necessary for counters and timers, and communication with peripherals

21-Control (29)

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CSR Instructions

Register operand
Instr.	rd	rs	Read CSR?	Write CSR?
csrrw	x0	-	no	yes
csrrw	!x0	-	yes	yes
csrrs/c	-	x0	yes	no
csrrs/c	-	!x0	yes	yes

SYSTEM

rd

instr

source/dest

source�uimm[4:0]

1110011

5

3

7

5

31

20

15

7

12

19

14

11

6

0

rs1

funct3

rd

opcode

csr

12

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CSR Instructions

Immediate operand
Instr.	rd	uimm	Read CSR?	Write CSR?
csrrwi	x0	-	no	yes
csrrwi	!x0	-	yes	yes
csrrs/ci	-	0	yes	no
csrrs/ci	-	!0	yes	yes

SYSTEM

rd

instr

source/dest

source�uimm[4:0]

5

3

7

5

31

20

15

7

12

19

14

11

6

0

rs1

funct3

rd

opcode

csr

12

Zero-extended to 32b

21-Control (31)

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CSR Instruction Example

The CSRRW (Atomic Read/Write CSR) instruction ‘atomically’ swaps values in the CSRs and integer registers.

We will see more on ‘atomics’ later

CSRRW reads the previous value of the CSR and writes it to integer register rd. Then writes rs1 to CSR
Pseudoinstruction csrw csr, rs1 is �csrrw x0, csr, rs1

rd=x0, just writes rs1 to CSR

Pseudoinstruction csrwi csr, uimm is �csrrwi x0, csr, uimm

rd=x0, just writes uimm to CSR

Hint: Use write enable and clock…

21-Control (32)

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System Instructions

ecall – (I-format) makes requests to supporting execution environment (OS), such as system calls (syscalls)
ebreak – (I-format) used e.g. by debuggers to transfer control to a debugging environment

fence – sequences memory (and I/O) accesses as viewed by other threads or co-processors

SYSTEM

0�0

PRIV�PRIV

ECALL�EBREAK

0�0

5

3

7

5

31

20

15

7

12

19

14

11

6

0

rs1

funct3

rd

opcode

funct12

12

21-Control (33)

Garcia, FA25