OCE Virtual Chiplet eco-systems

Title: System-Level Evaluation of Multi-Vendor Chiplets Pre-RTL

Presenter: Deepak Shankar | LinkedIn

Overview of Mirabilis Design

• EDA Software Company based in Silicon Valley
• Rrisk assessment, performance optimization and validation of specification
• Highly experience Management and Engineering team
• Over 150 man-years in semiconductors, automotive and Automotive
• VisualSim Architect –Design the Right product
• Simulation with System Modeling Components for Architecture Exploration
• Shift-Left to Shift-Right- A Total Solution
• System Optimization, Collaboration, Validation and Early Reference Designs

​

​

​

​

Mirabilis Design Inc.

2

2/5/2026

Networking

RF and Analog

Why System Modeling for Chiplet Design?

DSP

ΑΙ

GPU

DRAM

CPU

FPGA

μE

DSP

TDMA

Priority

EDF

WFQ

RISC

DSP

LookUp

Cipher

ΑΙ

DSP

CPU

GPU

μE

DDR

static

Workloads vs Performance- Concurrency and Contention

I/O

DSP

CPU1

CPU2

task₁

task₂

task₃

task₄

• Contention�- limited resources�- scheduling/arbitration

​

• Interference of multiple applications�- limited resources�- scheduling/arbitration�- anomalies

• Complex behavior�- input stream�- data dependent behavior

​

Unexpected or Expected?

System with faster Bus is slower in places

Unpredictable System Response

Spreadsheet- and Residency-based vs System Simulation

Divergence of analytical methods can lead to incorrect expectations

Challenges in the Design of Chiplets

• Latency, bandwidth and power consumption changes when transition from single-die to multi-die
• Impact of peripheral, memories and system cache position
• Scalable to support current and future applications?
• Support sufficient ports for application-specific topology?
• Distribution of accelerators and scheduling of tasks

CPU

CMN

DRAM

DRAM

CPU

CMN

UCIe CHI

CPU Load

1,2,4,8,16

CPU Cores

CPU

DRAM

DRAM

CPU

CPU

CMN

DRAM

DRAM

CPU

CMN

UCIe CHI

CMN

CMN

UCIe CHI

DDR Mem

System Model Requires Minimal Set of Settings

Comparing Different Configurations using UCIe Interface

All Die Adapters using PCIe 6.0

Die Adapters using PCIe 6.0 and Streaming Protocols (AXI)

Lower latency when using PCIe 6.0

Examining the Internals of UCIe IP

VisualSim UCIe IP Block Internals

UCIe System Modeling Component Verification

Note: Data verified against values in a presentation provided by Synopsys

Using the UCIe System Modeling IP in the assembly of SoC

• Core is an UCIe interface Module
• 4 processor Chiplets and 1 I/O Chiplet
• Each Processor Chiplet uses 4 UCIe Links.
• The I/O Chiplet uses 1 UCIe link.
• Workload
• Each Processor Chiplet has 4 traffic generators
• Send packets to the NOC UCIe block
• Transactions data flow:
• CPU -- > DSP
• DSP -- > GPU
• GPU 🡪 AI
• AI 🡪 I/O and CPU
• I/O 🡪 GPU

​

Experiment 1 - Varying Flit_size �

Table 1 : Base Parameters

Varying Flit_Size = Latency and Throughput across UCIe ports

Flit Size = 64 Bytes

Flit Size = 128 Bytes

Latency Plot for Each Chiplet

Observations on Experiment 1

• Latency Reduces Significantly – both Per Chiplet and across the UCIe ports when Flit_Size is doubled
• Throughput across the UCIe ports Increases Significantly - when Flit_Size is doubled
• Number of packets dropped also reduces when we increase the Flit_Size

​

Note : IO latency is measured across the PCIe, hence a difference is not observed when we vary the Flit_Size

Example Analysis

Multi-CPU Architecture

Architecture 1- Single Die with 1 Core per Cluster

SoC_with_A720AE_Demo_flow.xml

CPU

CMN

DRAM

Task Graph

Experiment 1 Results

• Beh_Flow_Latency – Shows the time it took to complete a task by CPU clusters (Chiplet) 1 and 2
• Latency plot – Shows the time taken by memory access requests sent out to the DRAM to complete
• Power_Plot – shows the power consumption across the die
• Text statistics – Shows detailed statistics across all cache levels (all chiplets), buses and DRAM

Thermal Characteristics: Heat(J) and Temperature (°C)

With poor cooling

Time_to_Reduce_1_Degree = 1.0

With better cooling

Time_to_Reduce_1_Degree = 1.0e-8

Heat (J) is lower with better cooling

Temp (°C) is lower with better cooling

Architecture 2: Multiple Ports between Dies

SoC_with_A720AE_4Clusters_UCIe_Demo_flow.xml

CPU

CMN

DRAM

Task Graph

UCIe Links

Die 1

Die 2

Experiment 2 Results

• Memory_Distribution_Percentage to increase DRAM accesses to other DRAM’s
• Increase the number of Cores per cluster from 1 to 16
• Experiment Routing Table to create the best route with minimal bottleneck

​

​

Power has gone up per die as we have more components per die

Comparing Single vs Multi-Die Latency

• Comparing Memory address distribution = 0% vs 40.0%
• Increase the address distribution percentage
• Task latency increases as data from DRAM in another die

OCE Virtual Chiplet eco-systems

Title: System-Level Evaluation of Multi-Vendor Chiplets Pre-RTL

Presenter: Deepak Shankar | LinkedIn