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SERVER

OCP NIC Community Update�February 2024

�����Sub-group Project wiki: https://www.opencompute.org/wiki/Server/NIC�

Mailing List: https://ocp-all.groups.io/g/OCP-NIC

NIC3.0

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Agenda

  • DSFF specification updates
  • SI workstream update
  • Mechanical tolerance analysis

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DSFF

Spans over two 4C+ connectors

(two SFF slots)

Regular and Tall options

160 Watt

x32 PCIe lanes

13% more board space

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Illustration only, silicon and I/O cage qty/placement not mandated in spec.

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Draft outline available on OCP Wiki page.

(157.54 mm)

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DSFF Spec Updates

  • WIP draft uploaded to wiki page
  • Feedback requested from community

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https://www.opencompute.org/w/index.php?title=Server/NIC#Working_Draft_Docs

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** Do not implement products against WIP drafts.

** Requirements are subject to change without notice.

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Spec Updates

  • Separated pinout tables for SFF, LFF, +DSFF
  • PRSNTB[7:0] == 0b0100_0100 - DSFF
  • Nomenclature change -
    • “SFF” includes “TSFF”
    • “DSFF” includes “TDSFF”
    • Differentiated in thermal/mechanical callouts. Electrical is the same between the “normal” and “tall” versions
  • Clarify duplicated sideband pin usage for DSFF
    • Primary Connector sideband expected to be used on DSFF by default
    • Secondary Connector sideband is board specific, declared in 0xC1 OEM Record
  • PCIe Link subdivision -
    • New OEM Record for PCIe Link subdivision (0xD0, 0xD1)
  • RBT
    • DSFF RBT timing budget needs to meet SFF

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DSFF Detection Flow

  • PRSNTB[7:0] == 0b0100_0100
    • Physically a DSFF
  • Read FRU EEPROM:
    • Read record 0xC0
    • Read record 0xC1 (DSFF)
      • Determine if this is a “monolithic” card or two-SFF cards
    • Read record(s) 0xD0, 0xD1 (PCIe link subdivision) -
      • Determine supported PCIe modes
      • Determine link to REFCLK/PERST association
      • BIF encoding
  • Assert BIF (if bifurcation is requested)

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DSFF SI Workstream

  • Upcoming Meeting Feb 8th @ 2PM PT / 4PM CT
    • Contact: Jason Rock at Dell for mtg invite

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  • Focused on establishing limits for PCIe® Gen 4, 5 for DSFF as well as Gen 6 for both SFF & DSFF

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  • Note all SI workstream participants must be with companies with active memberships to the PCI SIG & SNIA and shall maintain adherence to the OCP CLCA for all WIP material

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DSFF Mechanical Workstream

Mechanical Tolerance and Mating Force Analysis completed by Amphenol

    • 3 tolerance analyses completed
      • Interference when AIC inserts into dual S/M connectors
        • High DPPM predicted, suggested change in secondary connector key slot to reduce risk
        • Increase secondary key slot width from 1.85mm to 2.10mm
      • Overlap on gold fingers
        • DPPM of 960 predicted with 2.10mm key slot width change
      • Gap to next goldfinger
        • DPPM of 47 predicted with 2.10mm key slot width change
    • Mating Force Analysis
      • 2 connector mating force expectation = 1.1N * 168 = 184.8N Max
      • 2 connector mating force 3 sigma expectation = 2*(81.1+3*4.95) = 191.9N Max

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TA 1- AIC card inserts into connector

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TA 2 - overlap on gold finger

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TA 3 - gap to next gold finger

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