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Reconfigurable Computing

Prof. Dr. Vanderlei Bonato

The University of Sao Paulo (USP)

Institute of Mathematical and Computing Sciences (ICMC)

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Agenda

Introduction

Processor types

Transistor technology

Modern FPGAs

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(VAHID; GIVARGIS, 2002)

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Introduction

... communication also.

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Processor types

General Purpose processor

Von Neumann paradigm

Domain specific processor

Ex. Digital Signal Processor

Application specific processor (very specific)

Application Specific Integrated Circuit
Ex. Tensor Processing Unit (TPU)
Ex. Neural Processing Unit (NPU)

Reconfigurable processor

Ex. Field-Programmable Gate Array (FPGA)
Ex. Coarse Grain Reconfigurable Architecture (CGRA)

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The von Neumann Computer

Principle

In 1945, the mathematician von Neumann (vN) demonstrated in study of computation that a computer could have a simple structure, capable of executing any kind of program, given a properly programmed control unit, without the need of hardware modification

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Structure of von Neumann machine

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The von Neumann Computer

Structure

A memory for storing program and data

The memory consists of the word with the same length

A control unit (control path) featuring a program counter for controlling program execution

An arithmetic and logic unit (ALU) also called data path for program execution

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The von Neumann Computer

Advantage:

Flexibility: any well coded program can be executed

Drawbacks

Speed efficiency: Not efficient, due to the sequential program execution (temporal resource sharing).

Resource efficiency: Only one part of the hardware resources is required for the execution of an instruction. The rest remains idle.
Memory access: Memories are about 10 time slower than the processor

Drawbacks are compensated using high clock speed, pipelining, caches, instruction pre-fetching, etc.

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Domain specific processors

Introduced by Texas Instruments over thirty years ago

DSP, by design, performs math more efficiently, particularly for applications that include computation-intensive functions, such as analytics, FFTs and matrix math in a constrained environment.

Digital signal processor (DSP) has evolved in its implementation from a standalone processor to a multicore processing element

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Application examples from TI

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Application specific processor

Device is manufactured to design specifications

An Integrated Circuit is called an Application Specific Integrated Circuit (ASIC) if it is designed for a specific application.
ASIC Types

Full-Custom

design is done from scratch

Standard Cell

Based on predesigned logic gates

Gate Array

transistors are predefined in the silicon wafer

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Application specific processor

Implementation of a vN computer

if (a < b) then

{

d = a+b;

c = a*b;

}

else

{

d = a+1;

c = b-1;

}

At least 3 instructions
run-time >= 3*t_instruction

ASIC implementation:

The complete execution is done in

parallel in one clock cycle

run-time = t_clock= delay longest path

from input to output

The vN computer needs to be clocked

at least 5 time faster

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Reconfigurable Computing

Reconfigurable computing can be defined as the study of computations involving reconfigurable devices. This includes, architecture, algorithms and applications [Bobda 2007].

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Flexibility vs Efficiency

Source: [Adpted from Bobda 2007]

GPU /

Performance

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Temporal vs. spatial based computing

Temporal-based execution

(software)

Spatial-based execution

(reconfigurable computing)

Ability to extract parallelism (or concurrency) from algorithm descriptions is the key to acceleration using reconfigurable computing

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Reconfigurable devices

Field-Programmable Gate Arrays (FGPAs) are one example of reconfigurable devices
An FPGA consists of an array of programmable logic blocks whose functionality is determined by programmable configuration bits
The logic blocks are connected by a set of routing resources that are also programmable
Custom logic circuits can be mapped to the reconfigurable fabric

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Configuring FPGAs

[Maxfield’04]

FPGAs can be dynamically reprogrammed before runtime or during runtime (virtual hardware)

full
partial

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FPGA vs. ASIC Design Advantages�

FPGA Design
Faster time-to-market

No layout, masks or other manufacturing steps are needed

No upfront non-recurring expenses (NRE)

Costs typically associated with an ASIC design

Simpler design cycle

Due to software that handles much of the routing, placement, and timing

More predictable project cycle

Due to elimination of potential re-spins, wafer capacities, etc.

Field reprogramability

A new bitstream can be uploaded remotely

ASIC Design
Full custom capability

For design since device is manufactured to design specs

Lower unit costs

For very high volume designs

Smaller form factor

Since device is manufactured to design specs

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Current problems with �conventional computing

Technology scaling doubled the number of devices in an IC (processors, FPGAs, …, etc) every 2-3 years

Scaling also provided devices with reduced delay

frequency doubling (with aggressive pipelining)
increased power density

Increases in clock frequency slowed down (or stopped);

available devices are used to create multi-processor (multi-core) processors

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3D/FinFET transistor technology

Synopsys, “FinFET Technology – Understanding �and Productizing a New Transistor” - white paper, 2013

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Nanosheet FETs transistor technology (next generation)

Fig. 1: In nanosheet transistors, the gate contacts the channel on all sides (gate all around) and multiple sheets enable higher drive current than in finFETs. Silicon orientation differences (110 to 100) changes the carrier mobilities in the channel. Source: K. Zhao, IBM/IEDM Tutorial 2021

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Extreme Ultra Violet (EUV) technology

Finer resolution
Enable as the nanosheet FET IBM 2nm transistor

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Semiconductor development chain

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IC Foundries concentration�(16/14nm custo de ~12-15B USD)

Fonte: Global Semiconductor Alliance

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Source: https://www.semiconductors.org/wp-content/uploads/2022/11/SIA_State-of-Industry-Report_Nov-2022.pdf

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Report showing current state of the semiconductor industry

STATE OF THE U.S. SEMICONDUCTOR INDUSTRY

https://www.semiconductors.org/wp-content/uploads/2022/11/SIA_State-of-Industry-Report_Nov-2022.pdf

From Fabless to Fabs Everywhere? Semiconductor Global Value Chains in Transition

https://www.wto.org/english/res_e/booksp_e/07_gvc23_ch4_dev_report_e.pdf

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Current Transistors/chip

https://en.wikipedia.org/wiki/Transistor_count

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FPGAs with 3D/FinFET transistors

Stratix 10 (Altera/Intel)

14nm (Intel)
redução de 70% do consumo de energia
4 milhões de elementos lógicos (LEs)

Virtex UltraScale (Xilinx/AMD)

20nm (TSMC) – expanded also to 16nm – UltraScale+
redução de 50% do consumo de energia
4,4 milhões de células lógicas

Everest (Xilinx/AMD)

7nm
Adaptable Computing Acceleration Platform (ACAP)

Speedster22i HD (Achronix)

22nm (Intel)
1,7 millhões de LUTs
E-FPGA

Speedcore IP (eFPGA)
Allow to embed proven FPGA technology into ASIC

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Xilinx Everest: Enabling FPGA Acceleration With ACAP

The scope of the Everest project is impressive: 1,500 engineers working for four years to build a chip with fifty billion transistors, with total costs running over $1B.
The chip turns out 20 times the performance of the company’s existing FPGAs for AI applications.
The performance over a CPU ranges from 10X for image processing, to 90X for data analytics, to 100X for genomic sequencing.

Fonte: https://www.forbes.com/sites/moorinsights/2018/03/26/xilinx-everest-enabling-fpga-acceleration-with-acap/#9a88c52342ea

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ACAP TECHNICAL DETAILS�

An ACAP has – at its core – a new generation of FPGA fabric with distributed memory and hardware-programmable DSP blocks, a multicore SoC, and one or more software programmable, yet hardware adaptable, compute engines, all connected through a network on chip (NoC). An ACAP also has highly integrated programmable I/O functionality, ranging from integrated hardware programmable memory controllers, advanced SerDes technology and leading edge RF-ADC/DACs, to integrated High Bandwidth Memory (HBM) depending on the device variant.
Software developers will be able to target ACAP-based systems using tools like C/C++, OpenCL and Python. An ACAP can also be programmable at the RTL level using FPGA tools.

Sources:

- https://www.xilinx.com/news/press/2018/xilinx-unveils-revolutionary-adaptable-computing-product-category.html

- https://www.anandtech.com/show/12509/xilinx-announces-project-everest-fpga-soc-hybrid

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Discrete and Integrated platform

Source: PK Gupta

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Zynq UltraScale+ EG (Xilinx)

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ESL: desenvolvimento, integração e testes a nível de sistema

SDK for OpenCL (Altera)

Vivado (Xilinx)

HDL Coder (MathWorks)

MARTE, SysML (OMG)

BSV (BlueSpec)

www.forteds.com

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Aplicações

Robótica embarcada
Processamento de imagens
Sensores inteligentes
Aceleradores para computação de alto desempenho
Green computing
…..

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References

AMDA67 Amdahl, G. “Validity of the Single-Processor Approach to Achieving Large-Scale Computing Capability”, Proceedings of the AFIPS Conference, 1967.
CHRISOPHE BOBDA – “Introductions to Reconfigurable Computing – Architecture, algorithms and applications”- Springer, 2007, 359pg.
William Stallings. Computer Organization and Architecture, 8th Edition, 2010, 792p.

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