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Test Plans and Test Boards for Chips
BWRC
Do Not Distribute
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Motivation
There is a new procedure at BWRC for how boards are designed, fabricated and tested because:
This new procedure is an attempt to think ahead, catch problems, and ensure students understand the time required to prepare for and shepherd a board design through the entire vendor fabrication process.
For a chip design, there is one vendor and one process. For the test board, there are many possible variations and every board requires design of the process. In addition to many vendors being involved, there are several different types of vendors. Each vendor requires different documentation, design files, requests for quotes, purchase requests, sign-offs and humans to talk to. Human communication has to be done clearly, in Precise English, and in writing/pictures.
Overview of the New BWRC Test Board Process
1) Each board run will have two students assigned to it:
2) If the Chief Shepherd desires to enlist the services of BWRC Staff, there will be a staff member:
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Responsibilities
1) Chief Shepherd
2) First Mate
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Responsibilities
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Test Plans and Test Boards for Chips
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Board Fabrication Considerations
Vendors for bare board fabrication used by BWRC in the past:
Information to gather:
The Chief Shepherd and First Mate need to collect information to give to the Supreme Guru. Think through all these issues and choices:
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Board Fabrication Considerations (cont’d)
Board laminate choices:
Board stiffener requirements:
Controlled impedance traces:
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Board Fabrication Considerations (cont’d)
Board cap-and-plate choices:
Board blind via (i.e. “wrap-plating”) requirements:
Drilled hole density requirements:
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Board Fabrication Considerations (cont’d)
Component distance from edge of board:
Metal distance to the edge of the board:
Fiducials:
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Die Attach Considerations
Talk to the die-attach house to understand their requirements and/or interactions with designer’s constraints:
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Assembly (SMT and Thru-hole) Considerations
Having the assembly house buy your parts:
SMA connectors:
Spare Boards/Parts:
Documentation to give to the assembly house:
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Pastemask Stencil Considerations
BWRC has its own pastemask stencil frame, bought from Beam On. It lives on top of the reflow oven under the soldering bench
Alternatively, you can always have your assembly house order their own pastemask screen, but the assembly house will keep it
Note that not all of the footprints on your board will require solderpaste. Footprints that do not need solderpaste include:
Some components require pastemask openings to have a different shape than the footprint pad:
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Test Plans and Test Boards for Chips
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Package-attach and Assembly Requirements for Test Board to be Fabricated
Joint Chiefs:
Supreme Guru name/email/cell: Anita Flynn/aflynn@eecs.berkeley.edu/510-681-3931
Die/package name: OSCI-bear
Will there be more than one board design per panel (w/same layer stack-up, obviously … e.g. microstrip test board)?
Will a board be needed to test microstrip/stripline performance?
Will die be wirebonded, in a custom BGA package or flip-chipped (die-on-board)? If so, please describe: Yes, in a custom wirebonded QFN-48 package
How many copies of this package die are to be attached to the board? 1
Do any mechanical fixtures for a test setup need to be designed/fabricated?
Preferred board fabrication house?
Preferred wirebonding house? N/A
Preferred die attach house? N/A
Preferred assembly house? Digicom
Preferred pastemask stencil house? N/A (Digicom will order the pastemask stencils)
Other requirements (e.g. connectors, tented vias, vias-in-pads, diff pairs, vias-between-pads, ~3 mil circular pads, high-speed traces, etc.)?
Please write up a Test Plan on the following slides (insert new slides as needed) and do a Test Plan Review with First Mate and at least 2 other students. Then have your advisor review it for last-minute changes.
After Test Plan Review, list names of reviewers:
Name of advisor(s) and date he/she/they reviewed it:
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Package-attach and Assembly Requirements for Test Board to be Fabricated (cont’d)
How many boards do you want fabricated and how many of those do you want stuffed?
Do you want Digicom to buy parts for you?
Do you want Digicom to buy pastemask stencils for you?
Do you have a parts list with manufacturer’s part numbers?
If you have SMA connectors, do you want Digicom to do assembly using heat sinks screwed into the SMAs during the soldering step?
For footprint design in Altium, the Supreme Guru needs to understand your package’s pin-out:
What is the pin pitch? 0.4mm
What is the metallurgy of the pins? Gold over nickel (i.e. Digicom should use lead-free solderpaste for assembly)
What is the nominal width of each pin? 0.2mm
If you have a drawing of the package, please post it on the next slide. It’s a QFN-48 package. The drawing and URL are on the next slide.
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Package-attach and Assembly Requirements for Test Board to be Fabricated (cont’d)
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From Dan Frictman: “This is the package / pin-out mark-up we sent them.”
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This is the standard pin-numbering convention for a QFN-48 package. We need to know the mapping to signal name and electrical type (e.g. input, output, power, passive, etc.)
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Package-attach and Assembly Requirements for Test Board to be Fabricated (cont’d)
What surface plating do you want on your board? ENIG
Does your die/package have a cornermark? Yes, a corner cut, as shown on the previous slide.
What dielectric laminate material do you want for the board’s layer stackup? Megtron-6
The Supreme Guru needs to understand what the requirements are for decoupling capacitors for your chip.
How many power domains does your chip have?
List their voltages:
What is the worst case current for each domain? Worst case di/dt?
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Please attach a screenshot of your Altium schematic symbol here (delete this and paste your own, this is the symbol for the GPS chip):
These 3 sub-parts of the full Altium schematic symbol show the signal pins (there are 17 sub-parts, total, in the actual Altium symbol).
Package-attach and Assembly Requirements for Test Board to be Fabricated (cont’d)
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Steps in Testing (General)
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Steps in Testing
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RF Specific Test plan
Establish TX Output Matching Network
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Measure TX output
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RF Specific Test plan
Establish RX Output Matching Network
Measure chip RX
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RF Specific Test Plan
Measure chip TX to RX
To test the functionality of the ADC in the RX chain, the digital portion of the chip needs to be programmed to read out the values. More thorough BER/performance numbers also need the functionality of the digital baseband to process and export data into CPU or onto FPGA (need other designers’ input).
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From Felicia: design intent for external components for on-chip radio’s T/R switch & power amplifier:
Part considerations:
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Use 0603 size discretes to be able to remove/replace.
Taoglas GW.26.0112
Cinch 142-0701-801
Rcv
Tx
AnaTest1
AnaTest2
AnaTest3
AnaTest4
Required external components for the RF subsystem. The power amplifier will need its own LDO (3V):
Keystone 5009 (5x)
RF REF CLK
(2MHz)
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Board laminate: Megtron-6
Controlled impedance traces: Single-ended 50 ohm
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OSCI-bear-pcb will connect to a VCU-118 Xilinx board (same test setup as GPS-pcb)
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Test Plans and Test Boards for Chips
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Appendix A: Files Required by Each Vendor
Here is an example cloned repo for an Altium board:
The .OutJob is the GUI where one directs Altium to create the output files (e.g. ODB++ zip file, pick-n-place file, testpoints file, pdfs, etc.) Altium stores the generated output files in the Project Outputs directory (which gets overwritten each time). Hence, we have a convention of copying the requisite output file (and giving it a name beginning with the date in YYMMDD format), to the appropriate Files_SentTo_xxx directory.
An Altium Draftsman file is used to create a Fab Drawing. This must be given to the Board Fabrication House. It is the document that will travel with the board through every step in the factory. The pastemask stencil house will also ask for it.
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Files Required by Board Fabrication House
Quote returned from board house
The board house requires:
After the Quote Comes Back from the Board Fabrication House
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Files Required by Die-Attach House
The die-attach house requires:
Note: Quote had not been received back from Quik-Pak as of the time of this writing, but the quote will be stored in this repo.
After the Quote Comes Back from the Die Attach House
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Files Required by Assembly House
The assembly house requires:
After the Quote Comes Back from the Assembly House
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Files Required by Pastemask Stencil House
The pastemask stencil house requires:
Note: For Eagle1_revX2, we used the same frontside “partial, folded-up” pastemask stencils as was created for Eagle1_revX1. Separately, for revX2’s backside, we had Digicom order a pastemask screen that contained patterns for backsides of both eagle1_revX2 and eagle1_serdes_revX3.
After the Quote Comes Back from the Pastemask Stencil House
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Files Required by Machinist
The machinist requires blueprints
Quote hadn’t been received as of this writing, but would be stored in this repo.
The Supreme Guru will Interface with the machinist for mechanical fixturing for test setups:
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Test Plans and Test Boards for Chips
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Appendix B: Things to Consider Before Tape-out of the Die
Think through how you will test your die
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Things to Consider Before Tape-out of the Die (cont’d)
If you plan on probing your die with BWRC’s probe station:
Lorenzo Iotti has created some footprints for pad probing:
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Test Plans and Test Boards for Chips
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Appendix C: Packages and Die-on-Board Explained
There is a lot of lingo involved when a chip designer needs to communicate to a board designer. This appendix defines the terms used in this Test Plan Form.
What do we mean by package? interposer? flip-chip? die-on-board? chip-on-board? bump? ball? pad? footprint?
I use the word "ball" to refer to big solder balls that are put onto BGA packages, while I use the word "bump" to refer to the tiny solder bumps on your die when you receive your die from the foundry. A BGA package (ball grid array package) looks like this:
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Of course, BGAs are just one type of package. In this document, when I use the word “package” I’m thinking of all the different types of packages of commercially available chips. For example, there are a number of different packages shown in this photo of one slice of the Discrete Hydra 1.0 basestation:
Discrete Hydra’s ADC board
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Less commonly, you can by a “wafer-level-packaged chip” such as this part. For instance TI and Maxim have a number of chips which they sell in this sort of “package” (which is really un-packaged … i.e. no package at all). TI has a line of “tiny logic” in this form factor, and both companies sell small LDOs and switching regulators like this. This is just a silicon die with solder balls attached directly to a redistribution layer. Parts such as these typically come with a ball pitch of 0.4mm or 0.5mm … but never smaller than 0.4mm. Usually, these types of parts have only a few balls. The advantage of such an unpackaged chip is that it’s cheap and it saves space.
At BWRC, we wish to do something similar for the purpose of testing our custom dies. Mainly, it would be nice to not have to go through the expense and delay of getting a chip packaged by a packaging house such as Kyocera, etc. But before we get into some of the “die-on-board” attempts we’ve been doing at BWRC recently, let’s go back to wirebonding and BGAs.
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A number of BWRC projects have used wirebonded die. For instance, on this frontend receiver board for Discrete Hydra 1.0, there are 4 GaAs chips (LNA/downconverters) which are wirebonded directly to a printed circuit board (this could be called chip-on-board).
Discrete Hydra 1.0 receiver board back side with packaged parts:
The board’s top side has laser-etch cavities that these die get glued into (which makes the wirebonds as flat and short as possible for least inductance):
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Another example is this BROOM (Berkeley Resilient Out of Order Machine) die, also wirebonded directly to a printed circuit board:
Die photo
Glop-top (a type of epoxy) was poured over these wires after this wirebonding step to protect the fragile wirebonds from damage.
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This white printed circuit board holds a glop-top die (Hurricane1) which was wirebonded similarly to the BROOM chip:
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Other BWRC chips were packaged by a packaging house after the foundry run. For instance, this CRAFT2 chip was put in this BGA package after a TSMC run. The test board was designed at BWRC and the package was assembled onto the test board by our local assembly house, Digicom:
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What does it mean to have a die “put into a BGA package”? It can mean a number of different things. Internal to the package, the die could have been wirebonded or it could have been “flip-chipped”. Flip-chipped means that the die came out of the foundry with tiny bumps on a very tight pitch … and then an interposer (fine-pitch) board was fabricated and the die was flipped over and solder-attached to the interposer board. Then underfill (a type of epoxy) was injected under the die. And then a cap (or some molded glop-top, another type of expoxy) was used to cover the die. And then big bumps on a large pitch (> 0.4mm) were attached to the bottom side of the interposer board. This BGA packaging is typically done overseas by specialty packaging houses (Keyocera, Amkor, etc.). It can be fairly expensive and those packaging houses primarily do large volumes. Intel, ST and other companies also might have in house BGA packaging.
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This slide and the next 3 slides show screenshots of layout for 4 layers of a 4-layer interposer board (created for the Hurricane2 die). The layout tool is similar to a printed circuit board layout tool, but a fabrication house for these types of interposers can hold much tighter tolerances, line widths, hole sizes, etc. as compared to a conventional printed circuit board fabricator. The square in the middle signifies where the die would be attached to this interposer:
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Here’s an example of a recent BWRC project: the Hydra Head IC (16 75GHz receivers). After the die came back from the foundry with its bumps, an interposer was designed for the Kyocera interposer specs. Then the design was sent off to Kyocera for ~2-3 months fabrication time. When it came back, the interposer and die were sent to Quik Pak. Quik Pak did the attachment of the die onto the interposer (the interposer contains the 16 antennas on the top side and has balls on the bottom side. A board was designed and sent to Sierra for fabrication. Finally, the board was assembled (interposer plus SMAs and connectors by Digicom).
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To clarify some more lingo, let’s talk about bumps on a die and pads on a footprint. This is a SolidWorks model intended to explicitly show that the bumps on your die need to be designed in such a way that when the die attach house attaches your die (whether to an interposer or directly to a conventional printed circuit board) you better have an orientation mark … or at least some asymmetry in your bump pattern … such that your die won’t possibly be able to be attached in the wrong orientation to the footprint. This die has a corner mark, as does the footprint.
Die bumps
Footprint pads
Vias in the board layout to escape some of the pads
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Photo of the bump side of the Eagle1 die fabricated at TSMC. There’s no actual A1 bump, but the A2-B1 corner (at upper right in this photo) is marked on the board’s footprint (see next slide). Note, that this bump pattern is not rotationally symmetric, so it wasn’t possible to fit on the footprint incorrectly.
A27
B28
B1
A2
I use the phrase “die-on-board” to refer to flip-chip attachment of a die directly onto a printed circuit board (as opposed to an interposer). The Eagle project is one example of a die-on-board project.
This is the Eagle1_daughter_revX2 board:
Corner mark
Close-up of the bottom right corner of the U5 footprint on Eagle1_daughter_revX2:
The blind vias within the footprint (from Layer 1 to Layer 2) are filled, capped-and-plated and then covered with soldermask.
The as-drawn metal for each bump’s pad was 72um and the as-drawn soldermask opening was 1:1 at 72um. The nominal bump diameter was 83um.
The bump pitch was 170um.
The metal plating is ENEPIG.
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A2-B1 corner
This is the Altium board layout. Eagle’s 692 bumps were designed such that signals only come out at the periphery. Interior bumps are grouped into same-net clusters. This enabled a printed circuit board process to have enough room to put a via between a 2x2 quartet of same-net pads. That plus some top-layer traces to connect a few nearby same-net pads, allowed for escaping all interior bumps to internal power and ground layers. Still, the vias had to be drilled with the smallest possible drill bit (6 mil diameter). This was a 16-layer board, 62 mils thick (as thick as can be if you want to drill 6 mil holes, because a mechanical drill bit can only drill a 10:1 aspect ratio).
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Eagle1 die-on-board
Here is a photo after die-attach (done by Jabil). Backside components had previously been assembled by Digicom (i.e. backside components were sent through Digicom’s solder reflow ovens). After this die-attach step, frontside components were then assembled by Digicom with hand soldering (the boards did not go through Digicom’s oven a second time). The board was specifically designed with no small parts on the top side … only connectors which have to be hand-soldered anyway.
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After the die attach step, underfill was injected under the die and then cured. Then frontside components were hand-soldered on:
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Jabil had warned us that previous customers trying to do similar die-attach processes had seen their dies pop off if their boards had bottom side FMC connectors. The Eagle1 board did have an underside FMC connector, so Jabil recommended that the board be 98 mils thick in order to prevent bending forces during insertion from damaging the die attach. Since the 6 mil drill constrained the thickness to be no larger than 62 mils, we designed the Eagle1 board such that a stiffener could be attached to the board and then removed (for testing access) after plugging into the FPGA:
Stiffener
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The stiffener was designed to be removable while still enabling the board to remain screwed into standoffs on the test plate:
That is, to make this die-on-board, no package, project work … the die and the board had to be specifically designed to take all these constraints into account. Since a board cannot be fabricated to the tight tolerances achievable with a Keyocera interposer process, the entire board fabrication and assembly process had to be designed together.