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Chapter 2 Modern CMOS technology

1. Introduction.
2. CMOS process flow.

NE 343: Microfabrication and thin film technology

Instructor: Bo Cui, ECE, University of Waterloo; http://ece.uwaterloo.ca/~bcui/

Textbook: Silicon VLSI Technology by Plummer, Deal and Griffin

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• In the simplest CMOS technologies, we need to realize simply NMOS and PMOS transistors for circuits like those illustrated below.
• Typical CMOS technologies in manufacturing add additional steps to implement multiple device V_TH, thin film transistors (TFT) in SRAMs, capacitors for DRAMs etc.
• CMOS described here requires 16 masks (through metal level 2) and >100 process steps.
• There are many possible variations on the process flow (e.g. LOCOS device isolation vs. shallow trench isolation).

n-MOS & p-MOS require different channel background doping and source/drain region doping.

In CMOS, the gate is no longer “metal”, it is heavily doped poly-crystalline Si with low resistance.

CMOS: complementary metal–oxide–semiconductor

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CMOS (n-MOS & p-MOS) reduces static power dissipation.

Because (e.g. for the inverter) there is no current flow from +V to GND since one of the MOS is always off.

The same inverter logic can also be realized by replacing the top PMOS with a resistor R (ON NMOS << R << OFF NMOS), but current flows when NMOS is on.

CMOS is required by logic circuits

Output = GND = 0 if any Input or both are +V = 1

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D

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D

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S

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N-MOSFET (field effect transistor) operation

Body (bulk Si) is commonly tied to ground (0V).

When the gate is at a low voltage:

• P-type body is at low voltage, source-channel-drain is N⁺PN⁺.
• If drain is positive bias (i.e. electrons flow from the source and ‘drained’ to the drain), the right side PN⁺ diode is in reverse bias.
• Left side N⁺P is in zero-bias, as source is usually connected to the grounded bulk Si.
• No current flows through the channel, transistor is OFF

When the gate is at a high voltage:

• Positive charge on gate of MOS capacitor.
• Negative charge attracted to the top surface just below the gate oxide.
• Inverts a channel under gate to n-type, source-channel-drain is N⁺NN⁺.
• Now current can flow through n-type silicon from source through channel to drain, transistor is ON.

Inverted to n-type

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P-MOSFET (field effect transistor) operation

Body tied to high voltage (= source voltage, supply voltage).

Gate low (grounded, which is lower than high voltage bulk Si): transistor is ON.

Gate high (same as bulk Si): transistor is OFF.

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Since voltage has only a relative meaning. This is equivalent to the situation of: grounded body/bulk Si, grounded source, negative (< 0V) drain voltage (so holes flow from source and ‘drained’ to drain).

Then transistor is ON when gate is negatively biased, and OFF when gate is grounded.

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Transistors as switches

We can view MOS transistors as electrically controlled switches, and voltage at gate controls path from source to drain.

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CMOS inverter

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CMOS NAND gate

Output = 0 only when both Inputs are 1

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Cross-section of the CMOS IC

This is what we are going to fabricate in this chapter.

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Fabrication “toolkit”

• Insulating Layers
• Oxidation, nitridation
• Deposition (LPCVD, PECVD, APCVD)
• Selective doping of silicon
• Diffusion (in-situ doping)
• Ion implantation
• Epitaxy (in-situ doping)
• Material deposition (silicon, metals, insulators)
• LPCVD
• PECVD
• Sputter deposition
• Patterning of Layers
• Lithography (UV, deep UV, e-beam & x-ray)
• Etching of (deposited) material
• Dry etches—plasma, RIE, sputter etch, DRIE
• Wet etches—etch in liquids, CMP etc

LPCVD: low pressure chemical vapor deposition.

PECVD: plasma enhanced CVD.

APCVD: atmospheric pressure CVD

RIE: reactive ion etching

DRIE: deep RIE.

CMP: chemical mechanical polishing

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Chapter 2 Modern CMOS technology

1. Introduction.
2. CMOS process flow.

NE 343 Microfabrication and thin film technology

Instructor: Bo Cui, ECE, University of Waterloo

Textbook: Silicon VLSI Technology by Plummer, Deal and Griffin

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Substrate selection: moderately high resistivity (lightly doped, 10¹⁵cm^-3), (100) orientation substrate (better Si/SiO₂ interface than other orientations), P type.

Start from low doping, then dope P-well and N-well by ion implantation that is much better controlled than substrate doping (done during crystal growth).

Wafer cleaning, thermal oxidation (≈ 40 nm, using O₂, or H₂O generated from H₂ and O₂ reaction, cleaner than H₂O vapor from boiling water), Si₃N₄ LPCVD (≈ 80 nm), photoresist spinning and baking (≈ 0.5 - 1.0 μm).

Choosing the substrate and active region formation

Nitride has high tensile stress, oxide has compressive stress. The two stress can balance/compensate each other to reduce stress in Si that may cause defects in Si.

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LPCVD nitride: 3SiH₄+4NH₃ → Si₃N₄+12H₂, 800^oC.

LPCVD: low pressure chemical vapor deposition

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Mask #1 patterns the active areas. The nitride is dry etched.

Dry etch = plasma etch, reactive species are generated in a plasma (like arc discharge). E.g F is generated in CF₄ plasma. Atomic F is extremely reactive.

Si₃N₄ + 12F → 3SiF₄ (gas/volatile, pumped away) + 2N₂

Active region formation

Photolithography, nitride etching

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LOCOS isolation

Remove photoresist.

Field oxide is grown using a LOCOS process.

Typically 90min @ 1000˚C in H₂O grows SiO₂ ≈ 0.5 µm.

LOCOS: LOCal Oxidation of Silicon

http://en.wikipedia.org/wiki/LOCOS

Remove resist, thermal oxidation

Field oxide is partially recessed into the surface (oxidation consume some of the silicon)

Field oxides forms a lateral extension under the nitride layer – bird’s beak region

Bird’s beak region limits device scaling and device density in VLSI circuits!

Si₃N₄ is very dense material and prevents/blocks H₂O or O₂ from diffusion to the Si surface, thus no oxidation under nitride.

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Alternative process to LOCOS isolation:

shallow trench isolation with filled implants (here P⁺)

• Growth of pad silicon dioxide and deposition of silicon nitride as in LOCOS
• Implant trench to increase field threshold (for better device isolation) and growth of liner oxide for passivation and smoothing
• Trench fill with deposited oxide (not thermally grown oxide)
• CMP (chemical mechanical polishing) for planarization.

LOCOS:

Bird’s Beak problem, unsuitable for small device.

Note: this process added P⁺ impanation, slightly different from the process in textbook.

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P-well formation

Mask #2 blocks a B⁺ implant to form the wells for the NMOS devices. Typically dose 10¹³cm^-2 @ 150-200 KeV (very high energy).

(Implant dose is in cm^-2, doping concentration is in cm^-3)

Wet etch away Si₃N₄, spin photoresist, lithography, B⁺ implantation.

In ion implantation, positive B⁺ ions are formed by exposing the source gas containing B to an arc discharge.

Only B ⁺ is selected by a bending magnet to pass through a slit.

B ⁺ energy is high enough to pass through the field (LOCOS) oxide. But photoresist is thick enough to block the ions.

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N-well formation

Strip photoresist, spin resist and photolithography, ion implantation

Mask #3 blocks a P⁺ implant to form the wells for the PMOS devices.

Typically 10¹³ cm^-2 @ 300-400 KeV.

(P is heavier than B, so higher energy needed)

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N- and P- well formation

Remove resist and anneal

A high temperature drive-in produces the “final” well depths and repairs implant damage.

Typically 4-6 hours @ 1000˚C - 1100˚C or equivalent Dt.

(here D is diffusion coefficient, t is time)

Ion energy is ~100keV, much higher than energy needed to break 4 Si bonds (total 12eV), so ion implantation induces many damages.

B and P have similar diffusion coefficient, so similar final well depth.

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Threshold voltage (V_TH) adjustment

Mask #4 is used to mask the PMOS devices.

A V_TH adjust implant is done on the NMOS devices.

Typically 1-5 x 10¹²cm^-2 B⁺ implant @ 50 - 75 KeV.

Spin photoresist, photolithography, B⁺ ion implantation

Note: section 2.2.5 is skipped

Implant dose

Figure 2-22

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Threshold voltage (V_TH) adjustment

Remove resist, then spin photoresist, photolithography, As⁺ ion implantation

Mask #5 is used to mask the NMOS devices.

A V_TH adjust implant is done on the PMOS devices.

Typically 1-5 x 10¹² cm^-2 As⁺ implant @ 75 - 100 KeV.

Again, adjust V_TH by controlling implant dose Q_I.