Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device

¹ Department of Electrical Engineering, Indian Institute of Technology Bombay

² Department of Electrical Engineering, Indian Institute of Technology Kanpur

Abhishek Chanekar¹, Nachiketa Deshmukh^1,2, Abhinav Arya^1,2, Sandeep Anand¹

Presentation outline

• Motivation
• Literature Review
• Static I-V Characteristics and Power Loss Manipulation
• Desaturation Protection
• Proposed Methodology and effect of Parameter variation
• Simulation Results
• Experimental Results
• Conclusions

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Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device - Sandeep Anand

Motivation: Reliability enhancement

• Power electronics applications: Renewable generation, energy storage systems, battery chargers, electric vehicles, etc.
• Reliability of power converters: To avoid frequent maintenance and unplanned downtime
• Power Semiconductor Devices (PSDs): Most failure prone component
• Changing ambient and loading conditions: Thermomechanical stresses generated from the T_j swings are main reasons for the failure of PSDs
• Manipulating T_j profile: Reduction in stresses and increased lifetime of PSDs

• S. Yang, et. al., “An industry-based survey of reliability in power electronic converters,” IEEE Trans. on Ind. Appl., vol. 47, no. 3, pp. 1441-1451, May/June 2011.
• U.-M. Choi, et. al., “Study and handling methods of power igbt module failures in power electronic converter systems,” IEEE Transactions on Power Electronics, vol. 30, no. 5, pp. 2517–2533, 2015.

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Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device - Sandeep Anand

Literature review

Power loss manipulation using gate voltage: An effective method to reduce T_j swings

T_j swings manipulation

Thermal model from junction to ambient

• Cooling fan speed control
• Thermo-electric cooler module

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• Natural convection is a preferred choice in low power applications
• Use of advanced cooling systems not a viable solution

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Power loss in the PSDs

• Active and reactive power sharing in parallel connected converters
• Change in modulation strategy of the converter
• DC-link voltage regulation
• Switching frequency variation
• Independent power loss manipulation of each PSD is challenging

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• Gate resistance manipulation: Smooth control very difficult and increases system complexity
• Gate voltage manipulation

• Z. Ni, X. Lyu, O. P. Yadav, B. N. Singh, S. Zheng, and D. Cao, “Overview of real-time lifetime prediction and extension for sic power converters,” IEEE Transactions on Power Electronics, vol. 35, no. 8, pp. 7765–7794, 2020.

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Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device - Sandeep Anand

Static I-V characteristics

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Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device - Sandeep Anand

Power Loss manipulation

For a given I_D, value of V_Ch (R₂) and V_SCL (R₃) can be increased by reducing V_GS

Varying the value of V_DS, power losses can be manipulated at a given loading

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Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device - Sandeep Anand

Desaturation protection

• Gate-drivers have a safety feature of desaturation protection
• The increase in V_DS beyond the threshold limit during fault condition triggers the desaturation protection and turns-OFF the gate pulses.
• However, during loss manipulation, the reduction of V_GS causes increment in V_DS which may increase beyond the threshold limit of the desaturation protection.
• This would falsely trigger the desaturation protection and would cease the operation of the PSD unwillingly.

During power losses manipulation of PSD by reducing V_GS,

It is important to prevent the false triggering of the desaturation protection.

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Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device - Sandeep Anand

Proposed Methodology

• Initialization: Parameters R_P , V_Th , k, λ, and V_pro are obtained from device datasheet or characterization
• Change is load current is monitored to initiate the power loss manipulation
• ΔV_GS defines the steps in which power loss manipulation is done
• V_DS is calculated at each step and compared with the pre-set threshold value of desaturation protection
• The minimum value of V_GS is passed to gate driver once the V_DS exceeds V_pro

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Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device - Sandeep Anand

• For power loss manipulation, selected V_GS at a given I_D should ensure that the V_DS should be less than V_pro.
• However, the value of V_DS is affected due to variations in T_j which varies the parameters R_P , V_Th , and k
• In region R₁: Increase in T_j would increase R_P (0.92% / ^oC), and hence increase in V_DS
• Increase in T_j would decrease V_Th (-0.13% / ^oC) and k (-0.27% / ^oC)
• In region R₂ and R₃: parametric variation in V_Th and k may increase or decrease V_DS depending upon the operating conditions

Effect of Parameter variation on V_DS

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Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device - Sandeep Anand

• V_DS,max should be considered for selection of V_GS to prevent the false triggering of the desaturation protection
• V_DS,max keeps on increasing at lower V_GS and higher I_D

For a given value of I_D, the V_GS should be selected such that the V_DS,max is below the V_pro

Effect of Parameter variation on V_DS

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Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device - Sandeep Anand

Simulation results

• 350W, 48V i/p to 60V o/p, dc-dc boost converter, MOSFET: IPP60R105CFD7
• For each loading, V_GS is reduced from its recommended gate voltage to the lowest value possible without triggering the desaturation protection

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Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device - Sandeep Anand

Experimental results

• 350W dc-dc Boost converter developed in laboratory
• No significant change in power loss when V_GS reduced from 15V to 8V

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Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device - Sandeep Anand

Experimental results

• On identification of fault, the fault pin of driver transitions from logic high level to low level
• Minimum value of V_GS at 350W converter loading such that V_DS is less then V_pro
• Without temperature effect: V_GS = 5.5V
• With temperature effect: V_GS = 5.7V

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Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device - Sandeep Anand

Conclusions

• On-state V_DS of MOSFET is varied by changing V_GS to modulate the power losses.
• For varying load conditions, maximum range of V_GS is obtained to maximize the power loss manipulation of PSD without triggering the desaturation protection.
• For the selected PSD (and for many other commercially available ones), there is no significant change in the power loss for reduction in the V_GS from 15V to 8V.
• The on-state V_DS of the PSD depends upon the temperature and its effect should be considered while calculating the lower value of V_GS.
• During experimental validation, it is found that false triggering of desaturation protection occurs when temperature effect is not taken into account.

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Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device - Sandeep Anand

THANK YOU

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Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device - Sandeep Anand