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AXI-Stream

Проектирование цифровых вычислительных систем�Прутьянов В. В.

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AMBA

Источник: Introduction to AMBA AXI4

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AMBA: AXI-Stream

Источник: Introduction to AMBA AXI4

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AXI-Stream

AXI-Stream:

AXI4-Stream
AXI5-Stream

Wake-up signaling
Parity protection

IP для SoC:

ARM GIC-700 (контроллер прерываний) – коммуникация между компонентами
ARM MMU-700 (виртуализация I/O) – коммуникация между компонентами
ARM CMN-700 (интерконнект) – интерфейс для коммуникации между компонентами GIC-700

IP для FPGA:

Xilinx AXI DataMover – запросы на копирование и информация о завершении или ошибке
Xilinx AXI DMA – данные и запросы
Xilinx AXI Video DMA – передача видеопотока

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Основные сигналы

Сигнал	Источник	Ширина	Примечание
ACLK	Clock	1	Глобальный clock
ARESETn	Reset	1	Глобальный reset
TVALID	TX	1	Handshake
TREADY	RX	1	Handshake
TDATA	TX	TDATA_WIDTH	Целое число байт
TID	TX	TID_WIDTH	Data strea ID
TSTRB	TX	TDATA_WIDTH/8	Data or position byte
TKEEP	TX	TDATA_WIDTH/8	Transmit byte to dest.
TLAST	TX	1	End of packet
TDEST	TX	TDEST_WIDTH	Routing information
TUSER	TX	TUSER_WIDTH	User information

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Соединение

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Handshake signaling

For a transfer to occur, both TVALID and TREADY must be asserted. Either TVALID or TREADY can be asserted first, or both can be asserted in the same ACLK cycle.
TX is not permitted to wait until TREADY is asserted before asserting TVALID. Once TVALID is asserted, it must remain asserted until the handshake occur.
RX is permitted to wait for TVALID to be asserted before asserting TREADY. It is permitted that RX asserts and deasserts TREADY without TVALID being asserted.

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Clock and Reset

A single clock signal, ACLK, is used by each component. All input signals are sampled on the rising edge of ACLK. All output signal changes must occur after the rising edge of ACLK.
ARESETn is a single, active-LOW reset signal. The reset signal can be asserted asynchronously, but deassertion must be synchronous after the rising edge of ACLK.
During reset, TVALID must be driven LOW. All other signals can be driven to any value.
TX interface must only begin driving TVALID at a rising ACLK edge following a rising edge at which ARESETn is asserted HIGH.

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Термины

Transfer

A single transfer of data across an AXI-Stream interface.
A single transfer is defined by a single TVALID and TREADY signal handshake.

Packet

A group of bytes that are transported together across an AXI-Stream interface.
A packet can consist of a single transfer or multiple transfers.
Последний transfer пакета обозначается TLAST=1
Какие данные объединять в пакет определяет IP

Frame

A frame contains an integer number of packets.
A frame can have a very large number of bytes, for example an entire video frame buffer.
A frame is the highest level of byte grouping in an AXI-Stream interface.
Какие данные объединять во фрейм определяет IP

Data stream

The transport of data from one source to one destination.

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Термины

Transfer

A single transfer of data across an AXI-Stream interface.
A single transfer is defined by a single TVALID and TREADY signal handshake.

Packet

A group of bytes that are transported together across an AXI-Stream interface.
A packet can consist of a single transfer or multiple transfers.
Последний transfer пакета обозначается TLAST=1
Какие данные объединять в пакет определяет IP

Frame

A frame contains an integer number of packets.
A frame can have a very large number of bytes, for example an entire video frame buffer.
A frame is the highest level of byte grouping in an AXI-Stream interface.
Какие данные объединять во фрейм определяет IP

Data stream

The transport of data from one source to one destination.

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Пример: передача кадра видеопотока

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TKEEP and TSTRB

TKEEP

When TKEEP = 1, the associated byte must be transmitted to the destination
When TKEEP = 0, the associated byte is a null byte that can be removed from the stream

TSTRB

When TKEEP = 1, TSTRB indicates whether the associated byte is a data byte or a position byte
When TSTRB = 1, the associated byte contains valid information and is a data byte
When TSTRB = 0, the associated byte does not contain valid information and is a position byte

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TKEEP and TSTRB

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TID and TDEST

TID – Provides a stream identifier that can be used to differentiate between multiple streams of data that are being transferred across the same interface
TDEST – Provides coarse routing information for the data stream
Transfers that have the same TID and TDEST values are from the same stream

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Interleaving and Ordering

Interleaving:

Transfer interleaving is the process of interleaving transfers from different streams on a transfer-by-transfer basis
TX can interleave streams at source and an interconnect can interleave streams from multiple TXs at a point of convergence
RXs can be designed to accept any number of interleaved streams or a limited number of interleaved streams

Ordering:

The AXI-Stream protocol requires that all transfers remain ordered
The reordering of transfers is not permitted

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Пример: interleaving by interconnect

TX A

TX B

A4S

Interconnect

RX

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Тестирование

// Send 1 AXI4-Stream transfer

task automatic axis_send;

input [DATA_W-1:0] data;

begin

wait (rst_n);

@(posedge clk);

tdata <= data;

tvalid <= 1'b1;

@(posedge clk);

while (!tready)

@(posedge clk);

tvalid <= 1'b0;

end

endtask

// Receive 1 AXI4-Stream transfer

task automatic axis_recv;

output [DATA_W-1:0] data;

begin

wait (rst_n);

@(posedge clk);

tready <= 1'b1;

@(posedge clk);

while (!tvalid)

@(posedge clk);

data = tdata;

tready <= 1'b0;

end

endtask

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Verification IP

Разработка тестбенчей для каждого модуля с нуля может приводить к потере времени и ошибкам
Переиспользовать можно не только синтезируемое IP, но и верификационное IP (VIP)

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Литература

AMBA AXI-Stream Protocol Specification