VLSI Design – 18EC72

Module 2

Fabrication: CMOS Fabrication and Layout, VLSI Design Flow, Introduction, CMOS Technologies, Layout Design Rules,

(1.5 and 3.1 to 3.3 of TEXT2).

MOSFET Scaling and Small-Geometry Effects, MOSFET Capacitances

(3.5 to 3.6 of TEXT1).

Fabrication

(1.5 and 3.1 to 3.3 of Text 2)

nMOS Fabrication

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Step 1:

• Process is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the required p-impurities are introduced as the crystal is grown

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Step 2:

• A layer of silicon dioxide (SiO2) is grown all over the surface of the wafer to protect the surface
• Act as a barrier to dopants during processing, and provide a generally insulating substrate on to which other layers may be deposited and patterned

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Step 3:

• The surface is now covered with a photoresist which is deposited onto the wafer and spun to achieve an even distribution of the required thickness

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Step 4:

• The photoresist layer is then exposed to ultraviolet light through a mask which defines those regions into which diffusion is to take place together with transistor channels

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Step 5:

• These areas are subsequently readily etched away together with the underlying silicon dioxide so that the wafer surface is exposed in the window defined by the mask

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Taranath H B

Step 6:

• Photoresist is removed and thin layer of SiO2 is grown over the entire chip surface and then polysilicon is deposited on top of this to form the gate structure

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Step 7:

• Photoresist coating and masking allows the polysilicon to be patterned and then the thin oxide is removed to expose areas into which n-type impurities are to be diffused to form the source and drain

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Step 8:

• Thick oxide is grown over all again and is then masked with photoresist and etched to expose selected areas of the polysilicon gate and the drain and source areas where connections are to be made

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Taranath H B

Step 9:

• The whole chip then has metal (aluminum) deposited over its surface. This metal layer is then masked and etched to form the required interconnection pattern

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nMOS Process

• Mask 1: To expose Si surface where paths in the diffusion layers or gate areas of transistors are required. Also called Thinox.
• Mask 2: Pattern ion implementation where depletion mode devices are to be produced-self alligning.
• Mask 3: Deposit polysilicon and remove thin oxide layer where it is not covered by polysilicon.
• Mask 4: Grow thick oxide over all and etch for contact cuts.
• Mask 5: Deposit metal and pattern.
• Mask 6: Required for overglassing process step

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Complementary MOS fabrication

• CMOS Technology depends on using both N-Type and P-Type devices on the same chip.
• The two main technologies to do this task are:
• P-Well (Will discuss the process steps involved with this technology)
• The substrate is N-Type. The N-Channel device is built into a P-Type well within the parent N-Type substrate. The P-channel device is built directly on the substrate.
• N-Well
• The substrate is P-Type. The N-channel device is built directly on the substrate, while the P-channel device is built into a N-type well within the parent

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• Two more advanced technologies to do this task are Becoming more popular for sub-micron geometries where device performance and density must be pushed beyond the limits of the conventional p & n-well CMOS processes
• Twin Tub
• Both an N-Well and a P-Well are manufactured on a lightly doped N-type substrate.
• Silicon-on-Insulator (SOI) CMOS Process
• SOI allows the creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate.

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CMOS P-well process

Steps :

• N-type substrate
• Oxidation, and mask (MASK 1) to create P-well (4-5μm deep)
• P-well doping

P-well acts as substrate for nMOS devices. The two areas are electrically isolated using thick field oxide (and often isolation implants [not shown here])

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SiO₂

Steps :

• Remove p-well definition oxide
• Grow thick field oxide
• Pattern (MASK 2) to expose nMOS and pMOS active regions
• Grow thin layer of SiO₂ (~0.1μm) gate oxide, over the entire chip surface
• Deposit polysilicon on top of gate oxide to form gate structure
• Pattern poly on gate oxide (MASK 3)

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Steps :

• Implant P⁺ nMOS S/D regions (MASK 4)

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Thick field oxide

P

N-type substrate

P⁺ implant/diffusion

P⁺ mask

Steps :

• Implant N⁺ pMOS S/D regions (MASK 5 – often the inverse of MASK 4)

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P

N-type substrate

N⁺ implant/diffusion

N⁺ mask

P⁺

N⁺

Steps :

• Oxide and pattern for contact holes (MASK 6)
• Deposit metal and pattern (MASK 7)
• Passivation oxide and pattern bonding pads (MASK 8)
• Two separate substrates : requires two separate substrate connections
• Definition of substrate connection areas can be included in MASK 4/MASK 5

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P

N-type substrate

P⁺

N⁺

N⁺ for N-substrate contact)

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P⁺ (for P-substrate contact)

V_SS

V_out

P channel

Device

N channel

Device

CMOS N-well process

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• An N-well process is also widely used

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N-well

P-type substrate

N⁺

P⁺

P⁺ for P-substrate contact)

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N⁺ (for N-substrate contact)

V_DD

V_out

P channel

Device

N channel

Device

Twin-Tub (Twin-Well) CMOS Process

• This technology provides the basis for separate optimization of the nMOS and pMOS transistors
• it makes possible for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned independently

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Inverter cross section

• In this diagram, the inverter is built on a p-type substrate

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Fig: CMOS flip-flop with two phase non inverting clock

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Inverter cross section

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Fig: Inverter cross section with well and substrate contacts

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Fabrication Process

• The fabrication sequence consists of a series of steps
• The inverter could be defined by a hypothetical set of six masks:
• n-well
• Poly silicon
• n+ diffusion
• p+ diffusion
• contacts
• metal

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• Different masks are shown below

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Fig: Inverter mask set

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Layout Design Rules

• Objective is to allow a ready translation of circuit design concepts
• Design rules are the effective interface between the circuit/system designer and the fabrication engineer
• Circuit designers want tighter, smaller layouts for improved performance and decreased silicon area
• Process engineers wants design rules that result in a controllable and reproducible process
• The simple lambda(λ) based design rules based on single parameter λ which leads to a simple set of rues for the designers and allows for scaling of designs to a limited extent

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Layout Design Rules

• set of design rules for layouts with two metal layers in an n-well process is as follows:
• Metal and diffusion have minimum width and spacing of 4λ
• Contacts are 2 λ × 2 λ and must be surrounded by 1 λ on the layers above and below
• Poly silicon uses a width of 2 λ
• Poly silicon overlaps diffusion by 2 λ where a transistor is desired and has a spacing of 1 λ away where no transistor is desired
• Poly silicon and contacts have a spacing of 3λ from other poly silicon or contacts
• N-well surrounds pMOS transistors by 6 λ and avoids nMOS transistors by 6 λ.

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λ- based design rules

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Fig: Simplified λ- based design rules

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Gate Layouts

• Simple layout style based on a “line of diffusion” rule that is commonly used for standard cells in automated layout systems

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• This style consists of four horizontal strips:
• metal ground at the bottom of the cell
• n-diffusion
• p-diffusion
• metal power at the top

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• The power and ground lines are often called supply rails.

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• Polysilicon lines run vertically to form transistor gates.

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• Metal wires within the cell connect the transistors appropriately

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Fig: Layout for an inverter

Example - Inverter

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Example- 2 input NAND Gate

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Example- 2 input NOR Gate

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Contact Cuts

• Three possible approaches –
• Poly to Metal then Metal to Diffusion
• Buried contact (poly to diff)
• Butting contact (poly to diff using metal)

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Normal Contact

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Buried Contact

• An extra mask step can be introduced to permit direct contact between polysilicon and silicon

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Butted Contact

• Polysilicon is aligned with the edge of the diffusion contact window, and metal connects the diffusion and polysilicon together

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Stick diagram

• Stick diagrams are used to convey layer information through colour code or monochromatic.
• The layout of stick diagram represents the topology of actual layout on the silicon.
• The stick diagram can be converted into mask layouts
• nMOS Design Style
• CMOS Design Style
• BiCMOS Design Style

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nMOS design Colour codes

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Metal 1

poly

ndiff

pdiff

Metal 2

Contact cut

Buried Contact

Implants

nMOS Design Encoding

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D

S

G

D

G

n-type enhancement

n-type depletion

S

S

nMOS Design Encoding

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D

S

G

D

G

n-type enhancement

n-type depletion

S

S

Procedure

1. Metal (Blue) Vdd, Ground rails in parallel allowing enough space between them
2. Thin oxide paths are drawn(Green) between the rails for inverter and inverter base logic
3. Contacts in black or brown are made
4. Inverter based logic comprises of a pull-up structure (depletion mode transistor) connected between Vdd and output and the pull-down structure of enhancement mode transistor connected between output and ground
5. Depletion layer are identified by dotted yellow lines
6. L/W ratios are to be identified for each transistors

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Examples - Inverter

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Vin

Vin

Vout

Vout

Example- 2 input NAND Gate

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A

B

Y

A

B

Y

Example- 2 input NOR Gate

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A

B

Y

A

B

Y

CMOS Design Colour codes

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Demarcation line

VDD or VSS Contact

Design Rules

1. Diffusion paths must not cross demarcation line
2. N-diffusion and P-diffusion lines/wires must not join
3. N and P features are joined by metal lines
4. Place crosses on Vdd and Vss rail to represent the substrate and p-well connections – 1 cross for every 4 transistors
5. Only metal and poly lines can cross demarcation line

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Example- Inverter

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Vin

Vout

Example- 2 input NOR Gate

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A

B

A

B

Y

A

B

Y

Example- 2 input NAND Gate

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A

B

A

B

Y

A

B

Y

Example- Boolean Expression

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Different layout style

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CMOS Technologies

• CMOS processing steps can be broadly divided into two parts.
• Transistors are formed in the Front-End-of-Line (FEOL) phase, while wires are built in the Back-End-of-Line (BEOL) phase

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Manufacturing Process involves�

• Wafer formation
• Photolithography
• Well and Channel formation
• Silicon Dioxide
• Isolation
• Gate oxide
• Gate and Source/Drain Formation
• Contacts and Metallization
• Passivation
• Metrology

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Layout Design Rules

• Layout rules, also referred to as design rules

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• The rules are defined in terms of feature sizes (widths), separations, and overlaps.

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• The main objective of the layout rules is to build reliably functional circuits in as small an area as possible

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Design Rule Background

• Well Rules
• Transistor Rules
• Contact Rules
• Metal to p-active (p-diffusion)
• Metal to n-active (n-diffusion)
• Metal to polysilicon
• Metal to well or substrate

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Fig: Subtrate Contact

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• Metal Rules
• Via Rules
• Other Rules
• Extension of polysilicon or metal beyond a contact or via
• Differing gate poly extensions depending on the device length
• Maximum width of a feature
• Minimum area of a feature (small pieces of photoresist can peel off and float away)
• Minimum notch sizes (small notches are rarely beneficial and can interfere with resolution enhancement techniques
• Micron Design Rule

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MOSFET Scaling and Geometry Effects

• The reduction of the size i.e., the dimensions of MOSFETs, is commonly referred to as scaling

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• There are two basic types of sizereduction stratergies:
• Full Scaling (Constant Field scaling)
• Constant Voltage scaling

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Fig: Scaling of a typical MOSFET by a scaling factor of S

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Full Scaling (Constant-Field Scaling)

• This scaling option attempts to preserve the magnitude of internal electric fields in the MOSFET, while the dimensions are scaled down by a factor of S.

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• The gate oxide capacitance per unit area is changed as follows

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Table: Full scaling of MOSFET dimensions, potentials and doping densities

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Constant Voltage Scaling

• All the dimensions of the MOSFET are reduced by a factor of S, as in full scaling.
• The power supply voltage and the terminal voltages remain unchanged

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Table: Constant voltage scaling of MOSFET dimensions, potentials and doping densities

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Table: Effect of constant voltage scaling upon key device characteristics

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MOSFET Capacitance

• The on-chip capacitances found in MOS circuits are in general complicated functions of the layout geometries and the manufacturing processes.
• Most of these capacitances are not lumped, but distributed, and their exact calculations would usually require complex, three-dimensional nonlinear charge-voltage models.

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Fig: Lumped representation of the parasitic MOSFET capacitances

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Oxide related capacitances

• The gate electrode overlaps both the source region and the drain region at the edges.
• The two overlap capacitances that arise as a result of this structural arrangement are called CGD (overlap) and CGS (overlap), respectively.
• Assuming that both the source and the drain diffusion regions have the same width W, the overlap capacitances can be found as

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• In cut-off mode , the surface is not inverted. Therefore, the gate-to-source and the gate-to-drain capacitances are both equal to zero
• Cgs = Cgd= 0
• The gate-to-substrate capacitance can be approximated by

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• In linear-mode operation, the inverted channel extends across the MOSFET, between the source and the drain.
• Cgb = 0

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Junction Capacitance

• consider the voltage-dependent source-substrate and drain-substrate junction capacitances, Csb and Cdb, respectively.

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• Both of these capacitances are due to the depletion charge surrounding the respective source or drain diffusion regions embedded in the substrate.

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Text Books

• 1. “CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo Kang & Yosuf Leblebici, Third Edition, Tata McGraw-Hill.
• 2. “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E. Weste, and David Money Harris4th Edition, Pearson Education.

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• Note : Images and figures have been taken from prescribed textbooks.

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Reference Books

• 1. Adel Sedra and K. C. Smith, “Microelectronics Circuits Theory and Applications”, 6th or 7th Edition, Oxford University Press, International Version, 2009.
• 2. Douglas A Pucknell & Kamran Eshragian, “Basic VLSI Design”, PHI 3rd Edition, (original Edition – 1994).
• 3. Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, TMH, 2007.

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